In this final section of our board fabrication unit, we are concentrating on ways in which the fabricator seeks to prevent defective product reaching you, the customer, and then looking briefly at ways in which the quality and reliability of a product may not be as good as expected. This information of the potential for failure will be a supplement to the detail in the unit on Failure mechanisms.
What are the types of defect that you might expect to find on a board, i.e what things might go wrong with materials or process to create a faulty product?
Use your workaday experience of boards, as well as your study of the module so far, to generate as complete a list as possible. As with any lists we ask you to produce, try and create some kind of structure by grouping together similar kinds of fault.
Review your answer as you continue to read this page.
The list that we have created will probably be different from yours, not least in its arrangement. However, if you feel that you have identified a type of defect that we haven’t listed, please do drop an email to your tutor. Note, however, that we have distinguished between a defect, which is something which can be measured or observed, and the fault cause which lies behind the defect, such as the quality of plating.
Our list divides broadly into three categories:
Considering each of these in turn, the most obvious immediate defects affect DC interconnection, and affect both tracks and vias:
By now, you should be able to identify at least some of the likely causes for each of these. There are also defects that affect high frequency performance, such as incorrect track impedance, dielectric thickness, and spread in dielectric constant.
Note that these types of faults are not equally easy to spot – whilst an open-circuit may be easily distinguished from a short-circuit, high-frequency characteristics need special equipment, and the measurement of leakage is highly dependent both on conditions and on how many potential paths there are for unwanted current.
Defects that can potentially cause faults often have the same causes, but at lower severity. Two examples:
Other examples include:
1 Delamination is visually apparent as a colour change, looking like a blister. It is not to be confused with normal processing variation – some inner layers have a streaked appearance, which is acceptable.
Whether or not these potential faults develop into permanent catastrophic faults will depend on the application.
Finally, we have created a short list of defects that might not be apparent to the fabricator, but that will have at least some effect on the subsequent assembly process. These include:
Which of these defects might, if undetected, have implications for the reliability of the board itself and the assembly for which it is the base?
What procedures should we use in combination to screen against these defects?
Review your answer as you continue to read this page.
The term ‘in combination’ used in the preceding activity is deliberate, as no single screening method will be effective:
So we have to use a combination of screening methods. Typically we inspect inner layers prior to lamination, inspect the final board, test the finished board for the intended connectivity and isolation, and carry out sample testing and process control to assure compliance with the other desired parameters.
Inspection falls into two areas, determining that the board is correct, both mechanically and visually. Mechanical inspection will normally be restricted to overall dimensions and check that routing and scoring have been carried out. The visual inspection is more searching, as this has to cover a range of possible defect types, and solder mask, peelable solder mask and legend prints may combine to obscure the underlying track.
Typically an inspector will take a view of the whole board, looking for overall problems with surface finish on conductors, solder mask and legend, and for gross misalignment of legend, solder mask, drilling and routing. These are all processes capable of having global offsets to the intended location. Visual inspection is also very good at picking up differences in colour, texture and surface finish which may indicate undesirable process changes or the presence of contamination.
The standard that is generally used for bare board acceptability is the set of criteria given in IPC-A-600. If you have access to a copy, this will illustrate for you many of the possible defects.
Given the nature of the surface, the use of automated optical inspection (AOI) for external visual inspection is far less common than is its use for checking inner layers before lamination. Not only is it cost-effective to check the inner layer before it disappears from view, but the flat surface offers good contrast between copper and laminate, and the thin copper normally specified creates patterns that will normally be very close in dimensions to those intended. As a result, quite unsophisticated algorithms can be used to compare the pattern achieved against that intended.
The correctness of interconnection pattern itself is assessed by a ‘bare board’ test. This term can mean only a partial test confirming the tracks on each outer surface without a check on inner layers and through-board connections, However, for boards containing many vias, a test which exercises the complete PCB structure is strongly recommended because of high cost penalty of assembling a faulty board. The valid point has been made that electrical test is now becoming much more important to meet the demands of greater product reliability and higher performance.
The earliest through-hole boards were tested with hard wired continuity testers, whose expensive tooling could only be justified for high-volume applications. The first machines using ‘universal fixturing’ were introduced in the early 1980s. Their ‘universal grid’ is populated with test points, originally placed on grids at 0.100 inch centres. Even that comparatively coarse grid will have 100 points per square inch, and a large grid may contain tens of thousands of points, although the number of test points actually used is just the number of nodes in the boards to be tested.
Connection between the board under test and the tester is made using rigid but flexible test pins as indicated schematically in Figure 1. An array of plates converts the fixed grid on the test bed to the positions on the board, so that it is no longer necessary to have test points on the same pitch centres as the tester.
These ‘bed-of-nails’ fixtures are very commonly found, and revolutionised board testing – in 1980, 10% of US boards were electrically tested; by 1988, over 75% were tested.
The increase in the use of multilayer boards with double-sided surface mount has dictated that both sides of the board be tested at one time. Typically, double-sided testers use a ‘clam shell’ construction, where two sets of probes are closed together around the board under test. The most flexible configuration uses universal fixtures both top and bottom, but simpler equipment may have a universal bed-of-nails underneath and a set of customised probes for the top surface.
The trend in board dimensions is inexorably downwards, and boards frequently require close test point spacing. Whilst this can sometimes be accommodated by fixture design, typically the solution has been to use testers with finer grids. When even this approach runs out of steam, the alternatives are to make special fixtures, at considerable expense, or move to a flying-probe tester.
Flying probe testers use probes that are moved across the circuit and test point-to-point2 in order to verify continuity and isolation. There are many approaches to the problems of arranging probes and board, particularly given the need to approach the board from both sides. You may like to carry out a web search for "flying probe test", as this will show many of the alternative approaches. Look particularly at the different ways in which manufacturers seek to increase the probing rate, and hence reduce the time taken. As you might imagine, it is the extended time to test that is the key disadvantage of these testers. For accurate probing, and the ability to test on fine pitches, down to 100 µm, these testers are substantially more capable than the bed-of-nails type.
2 Note that, in one respect, the flying probe is fundamentally different from the universal grid tester in that probes are not able to contact all networks simultaneously, so cannot measure the total leakage from a given network to the remainder of the board in a single measurement. Instead they are limited to measuring the insulation resistance between specific network pairs.
Because the flying probe system is very flexible, it should always be considered for board layouts that are subject to change or made only in small numbers. However, once manufacture reaches more than prototype quantities, some hard tooling will be necessary.
But is probing necessary at all? Although probing equipment has improved substantially, reliable on-target probing has been made more difficult by smaller dimensions and tighter tolerances, and merely probing the board can create unacceptable levels of damage – any probing operation will leave at least some evidence.
For this reason, a number of approaches for contact-less testing have been explored, using electron beams or non-ionising electromagnetic radiation, or capacitative or inductive methods. Cirlog, for example, scan across the entire surface of the board under test, and obtain a ‘signature’ of its displacement current. Faults are detected by comparing against data from known good boards.
The original continuity testers were driven by data netlists entered line by line, but early advances were to use a known good board first to set up the fixture, and later to act as a ‘golden board’ from which the tester could ‘learn’ the actual board pattern, and compare other boards in the lot with the sample board.
With increasing sophistication of both boards and CAD, board testing has reverted to being driven by the netlist data. Files are generated from the netlist, either to manufacture a fixture or to drive a flying-probe tester. The fixture data generation starts by sorting the X and Y locations to create the ‘personality plate’, the top plate in the fixture that matches the image of the board to be tested. The test points are then assigned to specific grid locations, representing the electronic interface of the test system. Once all test pins have been assigned to specific test grid locations, the drill files are created for the test plates. Most of these plates use a combination of G10 laminate and transparent polycarbonate plastic.
The most critical element in board test is aligning the board precisely to the fixture, and this becomes more and more important as feature size and pitch decrease. The designer should make available at least three non plated holes that can be used for test alignment.
Whilst the presence/absence of an intended track or its resistance are easy to detect automatically, many boards used for high frequency applications have tracks which are designed to have a particular impedance. This is normally confirmed by the use of time domain reflectrometry.
This test determines the reflection signature of the transmission line (two tracks measured with respect to each other, or one track measured with respect to the power/ground planes). Early TDR equipment measured dedicated test patterns, normally placed outside the working circuit. This meant undue reliance placed on the quality of design and consistency of manufacture. However, newer equipment permits testing of actual tracks on boards, and the trend is towards this direct approach.
IPC-9252 “defines different levels of appropriate testing and assists in the selection of the test analyzer, test parameters, test data and fixturing required to perform electrical test(s) on unpopulated boards and inner layers”, and is a good starting point for developing a test specification. Benke, in his article A Tutorial on Test Equipment and Methods which appeared in PC Fab in March 2002, recommended five best practices:
So far we have concentrated on aspects of board quality that are evident, but there are reliability-related aspects of board quality that aren’t immediately apparent. For example, the desire to ensure that clearances are sufficient. Here we have several approaches:
Whilst within the fabrication environment the use of X-ray equipment is generally limited to yield protection by ensuring inner circuit alignment during lay-up, the verification of isolation is well-established. Known as ‘high-potential’ (‘Hi-pot’) testing, this uses high voltages (typically 500 V and more) applied between insulated tracks or planes for a given period. Not only will this indicate that the distance between isolated features is sufficient, thus screening out spacing violations and layer-to-layer misregistration, hi-pot testing will also identify laminate voids and metallic contamination.
The ultimate ‘hidden feature’ is plating quality, although this is only one example of quality and reliability issues that relate to process control during fabrication. In order to demonstrate effective process control, test coupons are built into the board design, usually on spare material on the panel but outside the circuit area. These coupons can be removed from the board, and provide both something to test, destructively if necessary, and something to keep – proof if needed that the product met an acceptable quality standard, or at least a means of ‘backtracking’ to the quality of a particular batch.
What is built into a test coupon varies enormously between suppliers and products, but typically the test coupon will have layer markers to indicate that all the copper layers are present with the correct alignment, and other features that enable the fabricator to test the electrical and mechanical characteristics of a standard pattern. For example, there may be standard tracks for foil adhesion testing, and ‘daisy chains’ of plated through-holes, that can be used to estimate the average resistance of through connects, and subsequently temperature cycled to demonstrate reliability. A quick test, and one which is very common, is to section part of the coupon, so that the through-hole plating can be examined in detail.
Within the chemical processing environment of the fabricator, quality is much more than inspection, and the laboratory plays an important role in both process control and verification of quality. Included in their task are controls on the plating chemistry, involving both chemical analysis and plating tests.
The laboratory will also have facilities for carrying out mechanical tests, such as the peel strength of foil, some means of sectioning, to take photographs of structure and assess the thickness of plating, and equipment to carry out solderability testing, both on the materials as deposited and after artificial ageing.
In preparation for an audit visit to your supplier, explain to your Quality Manager some of the ways in which how quality and reliability should be built into the boards that your company is purchasing.
So far we have been looking at how boards are screened for defects; our focus now changes to three significant quality and reliability issues. They are not the only such issues, but have been selected because they represent significant hazards.
PCBs are exposed to thermal stresses, the most important sources of which are:
As mentioned in the Resource Booklet More about board materials, a fundamental property of most laminating resin-matrix materials is the reversible change of state which takes place at the so-called ‘glass transition temperature’ (Tg), above which the substrate has a much higher coefficient of thermal expansion (TCE) in the thickness (Z) direction than in the plane of the woven matrix cloth (the X/Y plane of the board).
Since above Tg the laminate TCE climbs sharply, and the copper plating of the hole ‘barrel’ has a much lower TCE, aggressive thermal cycles can result in large strains in the Z direction and, consequently, on the through-holes. The plating acts like a rivet, resisting this expansion, but the barrel is stressed and may crack, causing electrical failure.
Plated through-holes are thus the PCB features most vulnerable to damage from thermal cycling and the most frequent cause of printed circuit board failures in service. Figure 2 and the associated photographs show common failure locations.
Failure may occur in a single cycle or may take place by the initiation and growth of a fatigue crack. For high-aspect-ratio through-holes subjected to repeated thermal shocks from room temperature to solder reflow temperatures (220–250°C) during board fabrication and assembly, failures after as few as 10 thermal cycles have been reported.
The number of cycles to failure is related to the ductility of
the copper plating and, with current plating technology, stress-related
failures are only a problem for thick (>3.2mm) boards such as
those used for back-planes. ‘Press-fit’ connectors have
been used successfully to eliminate most of these problems.
There are many ways in which process defects can impact on the reliability of a through-hole connection. Most of these are summarised in Table 1.
|Characteristic||Process affected||Defect||Impact on reliability|
|adhesion between foil and laminate||PTH drilling||copper delamination||poor barrel plating
entrapment of plating chemicals
|lamination cure||multi-layer drilling||epoxy smear; rough hole walls||poor bond between barrel and inner plane|
|smear removal||barrel copper plating||copper plating voids||solder joint voids
|seeding for barrel plating||barrel copper plating||copper-laminate void||barrel copper crack
poor bond between barrel and inner plane
wrong speed/feed ratio
|PTH drilling||epoxy smear||non-uniform copper
|copper plating||low tensile strength
|barrel copper fatigue
A high-reliability piece of airborne equipment uses a 2.5mm thick 8-layer FR-4 board as a back-plane, to interconnect a number of subsidiary circuits.
Explain, using a diagram, why your quality manager is concerned when he learns that the equipment will be in an unpressurized part of the aircraft, and subjected daily to wide temperature excursions.
Surface flatness is important for the assembler for many reasons:
Whilst excessive flexibility (‘bendy boards’) gives trouble on some designs, most flatness problems come from bow (‘warp’) and twist. It is important therefore to specify the maximum pre-assembly distortion (bow/twist) allowable both for panel and individual boards. A typical requirement for surface mount boards is 0.4% of the largest dimension, which is more stringent than for conventional assembly (0.7%).
The forces which generate warp and twist are mostly produced by differences in TCE within the board, although component layout and density may contribute. In general, the tendency for a particular board to warp will depend on the mass of the copper planes and their balance about the theoretical centre line of the structure. This will be affected by how well the board fabricator is able to balance or equalise foil spacings in the laminate structure, as well as by the uniformity of metal distribution in the design.
Typical design strategies to minimise warp and twist include:
The requirement for flatness also has an effect on the specification for even coating of the solder mask, and has frequently resulted in the omission of component identification marking (‘screen print’), as even this thin layer may lead to open-circuit joints.
Board distortion is worst when the base laminate is heated above its glass transition temperature, which occurs during both lamination and reflow soldering. Stresses that have been ‘locked into the laminate’ are relieved while the resin is soft, allowing the supporting medium to relax. Stress that may result in non-flatness can be caused by unbalanced construction or any kind of non-uniformity in impregnation, laminating pressure or temperature. Even if apparently flat when supplied, stresses present may be sufficient to produce warping when the temperature rises above the Tg of the resin, as will happen during reflow.
Warp related to lamination or subsequent baking may be possible to cure by ‘flat baking’ under applied weight. However, twist induced by lack of symmetry in design or build, or by excessive cooling rates during lamination, may lead to a board with ‘memory’, whose twist (or warp) will start returning when simply left unrestrained for a day.
‘It is possible to cool a board in a laminating press, yielding an acceptably flat product, only to have it curl up like a potato chip when it goes through reflow or wave solder’
Kelly M Schriver
Most board manufacturers are conscious of the need to supply flat products, but are constrained by the design. If you can measure and define the average shape of the physical distortion which occurs during assembly, the designer and fabricator will probably be able to reduce the problem for the next build.
Although these processes don’t appear on many simplified flow charts, one has to remember that board processes involve extended immersion in various ‘nasty fluids’. In order to prevent subsequent problems, extended cleaning is always undertaken, generally followed by sufficient baking to remove the bulk of the moisture content. Getting the board clean and dry is particularly important for reflow soldering, as the vaporisation of trapped water during the soldering process may cause delamination.
Bare board packaging has to protect both against ionic contamination and the ingress of moisture:
In order to preserve board condition and solderability, suppliers should pack the clean, dry boards in vapour barrier bags and heat seal the closures. It is important to remove excess air at the time of closure, and a nitrogen purge can be beneficial. Boards can be packed individually or in multiples, as best fits the application.
Some recommendations from users are that:
3 Whether desiccant is desirable is open to debate – a desiccant bag can ‘sit around acting like a sponge if the pack is penetrated’.
For a 4-layer board, describe as many as possible of the controls which are used to maintain quality and consistency of product.
Based on our experience, the major factors that affect interconnect reliability are, in hierarchical order:
Level 1: Copper plating thickness/quality: uniformity; ductility; elongation; tensile strength
Level 2: Material: Tg; TCE; board thickness; hole diameter; number of layers; glass to resin ratio
Level 3: Surface finish; through-hole metallisation; foil thickness; construction; grid size
Level 4: Design: pads vs. no pads on inner layers; annular ring; pad clearance
Two additional major factors not normally included in studies to determine interconnect performance are:
Bill Birch on the IPC TechNet Forum, 23 Feb 1999