This part of the unit pulls together more advanced information on a number of fabrication topics. It is supplemented by two PDF files, in the first of which, Multilayer bonding – what’s it all about?, Geoff Layhe tries to demystify the lamination process. We strongly recommend that you read carefully at least the first six sections of that document (pp.1–20).
The topics fall broadly into two areas: under Plating issues, Copper distribution and balance, and Other processes, we concentrate on things of which you need to be aware on an everyday basis. In the second group, Techniques for size reduction, Alternative processes and Prototyping, we are ranging more broadly and giving a brief introduction to topics that will be revisited in our advanced module Technology awareness for EDR.
Bear in mind that board technologies are amazingly diverse, and are often customised for specific applications, so that all we can attempt in this module is to describe the most common methods and materials, and give you a context in which to consider fresh ideas and information. Especially if your company is operating at the ‘leading edge’, you must expect to keep on learning of new processes and variants throughout your working life.
Most (though not all) board fabrication sequences involve plating one material onto another. So far, we have indicated in our diagrams and descriptions that the coatings as-plated are level and even, and skated over the fact that real plating processes give variable results, especially in terms of the thickness of deposit. In the next two sections, we are considering first the reasons for variable plating thickness, most noticeably down holes, and then the rationale behind getting an even copper distribution and balance.
We have already seen that the amount of material deposited by electroplating is expressed by Faraday’s Law:
where W is the weight deposited; I is the current; T is the time for which current flows; A is the atomic weight of the material being deposited; Z is the number of electrons involved in the electrode reaction (valency); and F is a constant.
The weight of the plating on the cathode is thus a linear function of the product of time and current, typically expressed in ampere-hours1; the average thickness deposited will, however, also depend on the density of the material. The rate of deposition of the most common metals is shown in Table 1.
gm per amp-hour
amp-hour for 25 µm
1 This is a unit of practical size, rather than the much smaller SI unit, the ampere-second or Coulomb. You will also find the same term, often abbreviated Ah, used for the amount of charge in a battery that will support a current flow of one ampere for one hour. The milliampere hour (mAh) is a common measure of charge in laptop batteries, providing an indication of how long the computer should operate on its battery without having to be recharged.
Note that, in order to plate 25 µm of copper, one needs to apply 1.88 amps per square decimetre (ASD2) for 60 minutes. This relatively slow deposition rate means that plating is usually carried out as a batch process, although, as we will see later, some progress has been made towards implementing continuous horizontal plating lines.
2 As you may have noticed, ASD is also not an SI unit! However, it is a practical indication of the kinds of currents which are involved, and as such is commonly used. Typical processes run at 2 ASD, which sounds much more reasonable than 200 amps per square metre, or even its approximate equivalent of 20 amps per square foot (ASF), which is how they would express things in the USA. Note also that the area used in the calculation has to be the area being plated, which may be substantially less than the area of the laminate, depending on the process and the pattern.
How much current flows in the cell will depend both on the voltage applied and on the plating cell geometry. Figure 1 is a ‘polarisation curve’, which plots the current in a plating cell against the voltage. The part of the curve3 that we use, the metal deposition area, shows a significant increase of current with applied voltage.
3 A plot of current density, with current density on a logarithmic scale, but concentrating on the linear portion of the curve, is referred to as a ‘Tafel plot’: in 1905, Tafel showed that the over-voltage h in a cell with a high cathodic current is given by the empirical formula
The reason for there being what is called a ‘limiting current density’ 4 is that metal ions cannot be deposited faster than they can arrive at the cathode surface, and this limit is set by the plating bath parameters. If the applied voltage is increased beyond that limit, other reactions will start to occur, such as the evolution of hydrogen. This is usually avoided, not only because it reduces energy efficiency, but because the deposit becomes rough and powdery.
4 There are three major mechanisms by which metal ions reach the cathode surface:
The plating cell potential for any given current is the sum of several types of over-voltage and the ohmic drop in the electrolyte. This ohmic drop depends on the electrolyte conductivity and the distance between anode and cathode. Because both electrodes are good conductors, it can be assumed that the potential between them is the same everywhere. As a result, the current density at any specific local area of the electrode is a function of the distance to the opposite electrode. This effect is called the ‘primary current distribution’, and depends only on electrode geometry and electrolyte conductivity.
The thickness of the local deposit varies with the local time-current product so, as Figure 2 shows, the thickness of the plating can only be constant if the cell geometry creates an even current density.
When plating onto a flat laminate, a sufficiently parallel field can usually be obtained, but plating piece-parts or three-dimensional boards can present more of a challenge. Four general ways of improving the evenness of plating are described below:
All these methods need physical modifications to the plating bath. However, for the more usual PCB situation of a flat substrate, a very simple set-up will provide uniform plating, given attention to agitation. However, this uniformity only applies on a macro scale, and there are a number of causes of small-scale variation, particularly relating to plating down through-holes and vias. Some of these are design-related, and others can be tackled using plating bath additives.
Intuitively, it is easy to see that, the narrower a hole in relation to its width, the less access there will be for plating solutions, the higher will be the ohmic resistance of the path to the anode, and the more difficult it will become to get even plating down the bore of the hole. The measure we use for this is the ‘aspect ratio’. This is the ratio of the depth of a hole to its width: whilst the aspect ratio could be quoted in a number of ways, a fabricator will normally define it as the ratio of the board starting thickness to the nominal drill diameter (Figure 3).
Aspect ratio is a major factor in yields through plating processes, with a high aspect ratio leading to plating ‘voids’ that are not detectable until bare board test. This gets particularly difficult when the holes are small, when the thickness of internal plating becomes even more significant. We reduce the level of this problem partly by design but mostly by adjusting the process.
‘Throwing power’ is calculated as the ratio of the thickness of copper within the hole to the thickness of copper plated onto the surface during the same operation. Typically this ratio will be less than unity, due to the relatively poor access of plating fluids to the hole, and the lower current density within it. The ratio will reduce, to a lesser or greater extent depending on the process, as the aspect ratio of the hole increases (the hole becoming either narrower or deeper).
Because panel plating is carried out before imaging, and is applied to the whole surface, variations in thickness can be kept to less than 10%. However, it is still important to achieve good throwing power so as not to over-plate the surface in the process of getting the desired 25 µm minimum layer thickness in the hole.
With pattern plating, the plating occurs after the image has been created using resist. Patterns are rarely uniform, and may contain both isolated tracks and pads and ground planes. This leads to considerable differences in current distribution, which can result in the copper in isolated areas being substantially thicker compared with those near ground planes. Some of the design issues related to this will be considered later.
Getting an even coat is partly a matter of setting appropriate conditions, and partly of choosing the correct plating additives. We saw from the plot of cell current against voltage in Figure 1 that the part of the curve that we use for plating shows a significant increase of current with applied voltage. It is this curve that can be altered by adding various organic materials to the plating bath:
In writing this, we are not trying to make you into chemists! However, you should be aware than electrolytic plating of copper is not a simple matter of dissolving copper sulphate in dilute sulphuric acid and passing a current between electrodes!
One way to achieve good distribution is to reduce the current density, to perhaps only 15–25% of its nominal level. However, this reduces throughput and increases part cost. In order to plate more quickly, yet achieve high throwing power, there are two options:
The mechanism is that additives are preferentially desorbed from high current density areas during the reverse cycle, which suppresses plating during the forward cycle. The result is substantially improved plating thickness distribution, and sometimes a throwing power of over 100%.
Periodic pulse reverse plating gives excellent results but it does of course mean investment in more expensive power supplies. It also requires specific additives, and is not just a question of changing the plating conditions. As a result, many fabricators prefer to use conventional plating, but pay careful attention to conditions and plating chemistry in order to optimise the uniformity of deposit. As we will see later, there are design strategies that may be used to even out the variation in copper density and thus reduce the importance of the problem.
Conventionally electroplating was always carried out in vertical tanks, with boards moved from plating bath to plating bath by means of programmable hoists. This batch processing made it difficult to integrate within a continuous flow line, and a number of attempts have been made to produce a horizontal electroplating process.
The limitation is that a 60-minute process requires an over-long plating module, so that current density has to be increased substantially, perhaps up to five times greater than for vertical electroplating. This offered a number of challenges to the plating chemist:
These have been overcome by the use of pulse plating to improve throwing power, and by using an insoluble anode and replacing the copper in solution by other means.
The general concept of copper balance is to evenly distribute copper on both sides of the PCB, and also within each side. With outer layers, a balanced copper pattern is important for even plating distribution; for inner layers, the main consideration is to create a balanced lay-up, giving a board that will not warp during subsequent heat processing.
Figure 5 shows ‘before and after’ pictures of an internal PCB layer: before copper balancing the layer has areas with sparse copper tracking that will cause problems for the fabricator; after copper balancing has been added, the previously bare areas have been filled with isolated copper dots.
Plating thickness varies according to the presence or otherwise of adjacent features. In general, it may be said that the more areas you are trying to plate, the thinner the plating will be. Conversely, when plating isolated tracks, the plating thickness can be substantially greater than desired. As shown in Figure 6, although the process conditions are identical, the plating thickness on a track becomes progressively thicker as the track moves further away from other tracks. This can be explained in simplistic terms as being due to the isolated pad experiencing less competition for current and the availability of metal in the plating solution.
But does a thick track matter? Not from the point of view of conductivity, and the extra width will not matter if it is isolated. The main effect will be on the thickness of the solder mask coat: thick copper will give a locally thin coat, with the potential to break down. There is also the mechanical effect on the board, where unbalance may lead to subsequent warpage.
The magnitude of the difference between isolated pads and tracks close together is demonstrated clearly in Figure 7. Not only is the plating on the isolated pad much thicker, with a substantial degree of edge distortion, but the solder mask coating is very much thinner.
Most of the discussion so far has been about copper, but any plating process will have associated potential problems. For example, care has to be taken when tin-lead plating: as shown in Figure 8, over-plating of the etch resist can produce residues of photoresist under the plating ‘overhang’, which will result in unetched areas of foil.
You may have noticed the term ‘well-robbed’ in Figure 7. This is related to the copper thieves referred to earlier, but in this case the additional cathode areas are on the board, rather than in the plating bath. ‘Robbing’ describes the practice of attempting to even out copper distribution on the board by adding areas of spare copper, so that the electrolytic plating process can add equal amounts of copper across the board without creating a thicker copper deposit on less-populated areas. These areas of spare copper are isolated from each other and from any active tracks. Because they act by attracting excessive copper plating away from otherwise isolated tracks, these areas are referred to as ‘robber pads’ or ‘copper thieves’. (Figure 9) The patterns used vary, being sometimes arrays of dots and sometimes cross-hatching.
Explain to one of your colleagues why the thickness of the electroplated layer may vary across a board, the impact this may have on its quality and reliability, and the ways in which designer and processor will seek to combat this variation.
This view of other processes cannot look at all the possibilities, but considers the main issue of multilayer bonding before going on to consider vias. Where no further information is given, then you can assume that the basics given in PCB Fabrication Processes will suffice for this module, even if they don’t cover every aspect of the technology – this is not a comprehensive course on fabrication. If you want more detail, then you are strongly recommended to browse through Coombs 2001 and the archives of the PC Fab magazine.
Rather than describe this important topic in detail, we have chosen to give a substantial amount of information in Geoff Layhe’s resource booklet Multilayer bonding – what’s it all about? link This deals comprehensively with the topics of prepreg selection, lay-up and processing, and your understanding can be checked by answering the SAQ that follows.
Whilst we have included Sections 7 and 8 in the booklet, this is very much additional material, beyond the scope of the module. However, if you have come across signal integrity issues, and perhaps have studied our modules on that topic, you may find Section 7 of interest.
Explain to one of your colleagues how you would set about selecting the cheapest possible approach for a six-layer board, and describe the processes and procedures by which the component materials would be laid-up and pressed into a completed multilayer board.
The practicable limit for drilled holes is around 0.30 mm, below which the drill bits become very fragile. For small vias, etching and plasma techniques are sometimes used, but ‘laser ablation’ is the alternative to drilling which is finding favour, especially for blind vias. Focused laser energy is repeatedly pulsed at the material to be drilled, vaporising layer after layer until a hole is created.
There are two main types of laser in use:
High pulse power, combined with low average power, allows material to be removed without organic materials in the board burning and leaving a carbon residue.
If you would like to read more about laser drilling options (and this is a topic to which we shall return in Technology awareness for EDR) a good starting point would be Pierre Justino’s article A comparative review of laser manufacturing processes in the July 2002 issue of PC Fab (in the Past issues section at http://www.pcfab.com/).
So far in this module we have just looked at through vias, and contented ourselves with a mention of blind and buried types primarily as a preparation for Technology awareness for EDR. However, one important aspect that we need to consider at this point is what to do when you have a through via, but want the connectivity without there being a physical hole through your board.
The original reason for doing this was to seal the via to make electrical testing possible without loss of vacuum on the fixture – through holes may fill with solder during assembly, but this cannot be guaranteed, especially with small vias. There are a range of other reasons for wanting this sort of protection – David Vaughan’s article in the July 2002 issue of PC Fab identified the following:
The original way of protecting a via was ‘tenting’, using dry film solder mask, but there are actually three types of protected via:
Tenting is a reliable process, but needs thick dry film solder mask, which is bad news for fine pitch assembly. Dry film mask is also comparatively expensive. As a result, “most people have junked their dry film solder mask laminators” and the current preferred process is LPISM, with the vias plugged by a separate printing operation.
The most common plugging technique is to fill the holes from one side with solder mask material, using a conventional single-sided screen or stencil printing operation. Printing from both sides is not advised, as this will entrap voids in the hole barrel. Typically fabricators use low squeegee speeds, in order to allow the vias time to fill. If you would like to read more about via hole plugging, try David Vaughan’s article The Hows and Whys behind via hole plugging in the July 2002 issue of PC Fab (in the Past issues section at http://www.pcfab.com/).
This standard technique used for applying legend (otherwise known as nomenclature or ‘silk-screen’) is conventional screen printing, using either UV curing or thermal curing ink. The pattern required is created in the screen, which is able to have a fine mesh, because the inks used have very small particles (in contrast to solder paste!).
However, even with a fine screen, it can be difficult to obtain high definition, and care has to be taken during printing in order to prevent smudging and the transfer of unwanted material from the underside of the screen.
An alternative to this method, which produces far better results in terms of both feature definition and placement, is to use screen printing to apply an overall coat of photoimageable legend ink. This can even be done on two sides simultaneously, using the same equipment used to apply solder mask.
Compared with pattern printing, this process wastes more ink. Also the time to process is increased because of the additional process stages of drying, imaging, developing and curing, although the final cure can be combined with curing the solder mask. However, the photoimaging process gives better results, and is often used for smaller batches where the manufacture of custom stencils cannot be justified.
An alternative to both processes is to use ink jet technology to apply legend directly. This is described in Mike Seal’s booklet on Direct legend printing. link
Your latest surface mount design has many vias, and your test engineer is concerned that it might be difficult to ensure that the board is adequately held down by the vacuum fixture. Discuss the benefits and problems of the different options that are available.
In PCB fabrication processes we saw that the most commonly used photoresists are ‘negative’-working, which means they polymerise on exposure to ultraviolet light and hence become insoluble in a direct developer, so that non-polymerised resist can be removed by ‘developing’ to expose copper areas ready for electroplating or etching.
An alternative approach, shown schematically in Figure 12, uses a ‘positive’ working photoresist, which starts off insoluble in direct developer, but becomes soluble once exposed to ultraviolet light. When used for etching, this means that the copper pattern is the same as the artwork, rather than being reversed.
One of the uses to which positive working photoresist may be used is indicated in Figure 12. This uses the fact that the photoresist can be exposed on multiple occasions, removing additional photoresist each time, until the final stripping operation. This progressive removal of photoresist allows complex structures to be produced of which this figure is just one example.
Positive working photoresists have distinct advantages for aligning critical features, which is why they represent 80% of the photoresist used in semiconductor manufacture, but they are the exception rather than the rule for board manufacture. However, you will discover some applications during your studies of Technology Awareness for EDR.
A ‘smart-power’ circuit design has some conductor tracks which must be capable of handling high currents but other areas where fine pitch control ICs are to be mounted.
What are the implications for your choice of foil thickness, pattern definition method and manufacturing sequence?
If you were to choose a selective plating approach, what might be the advantages of using a positive working resist?
Given that electroless plating methods had succeeded in the difficult task of plating down through-holes, it is not surprising that, since as early as 1964, boards have been made by such plating processes, starting with a bare laminate. When electroless plating is used for this purpose, it is often referred to as ‘additive technology’.
There is, however, a major difference between the electroless plating used for through-hole metallisation, which deposits only a very thin layer of copper (0.3–3 µm) as against full electroless plating which has no galvanically-deposited element.
Compared to electrolytic plating, fully-additive technology has several advantages:
Added to the fact that copper is only deposited where it is needed, one might have imagined that additive processes would now be the most widespread. The reason why this is not so relates partly to the higher cost of the processes and partly to a number of process issues:
There are a number of fully electroless processes, which you can find described in Chapter 31 of Coombs 2001, and both panel-plating and pattern-plating variants. Of these, panel plating is most common, in combination with a ‘permanent plating resist’. That is, the plating resist, once imaged and cured, stays as an integral part of the board, and the pattern is plated inside the resist apertures, creating a flush surface, with copper and resist the same height as the laminate. Having this flatter surface reduces scratch damage, reduces the consumption of solder mask, and reportedly tends to minimise solder bridges, particularly for fine-pitch devices.
Although improvements in simulation tools have reduced the need for prototyping, at least of the breadboarding variety, there are occasions when physical boards need to be made quickly. And many people still maintain that “prototyping prior to committing to large volume runs can save you time and money”.
The alternatives are to pay a considerable premium for a fast service, or, if equipment is available, you can choose to ‘do-it-yourself’, using small-scale conventional equipment, perhaps using pre-sensitised laminate. This is an activity that anyone familiar with university laboratories will have seen.
There are few problems with single-sided and double-sided boards, but through-hole plating is a tricky process to control, and equipment for pressing multilayers is even less common. Nevertheless, some equipment manufacturers offer plant specifically aimed at this market. However, justifying its purchase, and training technicians to use the equipment, generally demands reasonable numbers of prototypes, so most companies prefer to buy themselves a fast service.
Carry out a web search using search terms such as "Rapid PCB prototyping" and "PCB prototyping" + equipment, to try and establish:
Review your answers as you read the remainder of this page.
Typically the standard turnaround for board fabricators is 5 days, but this can be reduced to as little as 12 hours, depending on the complexity of the board, and in particular the number of layers and the finishing processes required: bare board testing, legend print and profiling are all processes that absorb time and which it may be possible to omit for electrical prototypes.
Of course, if the prototypes are required for checking mechanical fit and other aspects of manufacturability, the final version will be needed. However, at that stage the fastest service is generally not required, because the associated mechanical items typically take longer to prototype.
The turnaround time will, of course, include the pre-production work necessary at the board fabricator, adjusting track widths and so on in order to ensure that the board that leaves the fabricator meets the user’s requirements. This is often a stage where problems add substantially to the overall lead time, as you will discover if you read the section on Design for Fabrication in our Design for eXcellence module.
As well as ‘fast-tracking’ a board through a conventional fabrication line, there are two technologies that are promoted for prototyping purposes. The longest standing of these is available from LPKF (http://www.lpkf.com/) and T-Tech (http://www.t-tech.com/). Although the companies are independent, the technology is similar, using mechanical milling to remove unwanted copper on clad laminate. The end mill head can also be used for drilling and contour routing.
Conceptually simple, this system is best suited to applications with relatively broad tracks and a restricted number of drill sizes, since the tools are generally changed by hand and then need alignment. However, using high-speed motors, the LPKF system can achieve track widths down to 100 µm, and laser technology can be combined with the process to produce track/gap of 60 µm/40 µm.
Basically mechanical, and aimed at the double-sided board prototyping market, the original T-Tech process used eyelets, socket pins and via pins to establish connectivity. However, this approach has limitations, except for breadboarding, and both T-Tech and LPKF offer small-scale through-plating.
The LPKF system also has add-ons for dispensing, inspection and solder resist mask. In many ways it appears the system is being forced down the route of producing a close equivalent to a conventional board, though without the need for many of the chemical processes that discourage companies from setting up a prototype board fabrication shop.
An alternative approach, developed by Sigtronics as their ‘Kwikboard™’ printer (http://www.kwikboard.com/) also uses an engraving head, but cuts the tracks into bare laminate, filling the engraved pattern with a conductive polymer and curing this, creating a solderable track. By drilling holes with the engraving head, and filling the patterns from both sides of the board, using a squeegee to wipe the polymer ink over the surface and remove the excess, conductive through-holes can also be provided. Although originally developed as a method for PTH prototyping, this technology has also been extended to multilayer fabrication.
Whilst the combination of milling and conductive polymers makes Kwikboard compatible with an office environment, there are significant differences in conductivity between the polymer and normal foils. If the requirement is for a board that as nearly as possible approaches a conventional board, then the engraved foil processes would be favoured. However, it is significantly more difficult to achieve quality cutting in foil than in laminate, because of its ductility, and the complete removal of substantial areas of foil extends the processing time.
Perhaps the best long term approach for prototyping is to use the facilities at a dedicated fabricator, but employ technology such as ink-jetting and laser direct imaging to short-circuit some of the process steps. At the same time, by integrating the CAD system more effectively with the fabricator’s CAM, it may be possible to cut out many of the delays in the processes of converting concept to reality.
[ back to top ]