PCB fabrication processes

In the first part of this unit we concentrated on the sequence of processes: the aim now is to give you more understanding of the processes themselves.

As you read this section, please think about the process sequence and be sure you know where the process is used within board manufacture. We have tried as far as possible to describe the processes in the sequence experienced by a typical board, but there can be some variation, depending on the exact process used. Knowing the normal sequences will also greatly help you when you visit a factory, because the physical arrangement of many factories does not mirror the process sequence.

Board cleaning

The need for cleaning arises because process blanks may easily get contaminated during storage and handling. Oils and acids from finger grease, for example, can have a deleterious effect on subsequent processing, and dust and other deposits also need to be removed if high yield is to be obtained.

The board cleaning operation is vital to board quality, because the adhesion of the photosensitive films and resists is essential to produce well-defined copper features. The process needs both to remove the thin layer of surface oxide on the copper, and roughen the surface slightly. Three ways of cleaning are used, the first two of which are mechanical scrubbing methods:

Brush scrubbing or ‘standard brushing’, uses rotating wet brushes with abrasive particles. Brush scrubbing tends to impart stress to a thin core material by deforming it, so its use is normally restricted to cleaning outer layers. Brush scrubbing can also produce a surface that is not compatible with fine-line circuit designs

Pumice scrubbing, using brush or jet, is becoming more common because it creates minimal distortion and most high technology pumice machines will scrub cores down to 0.1 mm thick. Pumice, a volcanic material, starts as a solid foam whose pores are made of very thin layers of a glass that is hard and resistant to chemical attack and consisting mainly of silica. Powdered and formulated into a slightly acidic slurry, the mechanical movement across the copper surface removes a thin uniform layer of oxide and copper, whilst the action of the pumice particles creates a microscopically rough surface of virgin copper

Inner layer blank entering pumice cleaning machine

Inner layer blank entering pumice cleaning machine

Chemical cleaning, using a micro-etch) is normally chosen for cores less than 0.1 mm thick and for materials with coarse weave patterns (such as PTFE).

An alternative which is gaining in popularity is to avoid cleaning altogether by specifying ‘reverse-treated’1 foils, which do not require surface preparation because they have rough surfaces on both sides. The processes are proprietary but complex – details of this type of product can be found at http://www.gouldelectronics.com/ under RTC.

1 The Gould web site says that “Reverse-treated copper foil is manufactured by applying copper nodularization, brass thermal barrier and passivation to the shiny smooth side of the foil rather than to the roughened matte side of the foil as is done when manufacturing conventional or standard copper foil. A thin layer containing only passivation or antioxidants, which is normally applied to the shiny smooth side of standard foils, is applied to the roughened matte side of reverse treated foil. The fully treated side is laminated to a prepreg leaving the roughened matte side of reverse treated foil available for inner-layer processing.”


For single-sided boards, and the majority of PTH and multilayer applications, drilling is carried out by mechanical means, using tungsten carbide-tipped drills. Although now a very highly mechanised process, the largest single component of board cost is still usually in drilling holes. CNC drilling machines have been developed to give:

Multi-spindle operation

Automatic drill change

Rapid drill table movement

Accurate drill table positioning

Drill wear, break and run-out detection systems.

Section showing poor drilling

Section showing poor drilling

The need to drill fast and accurately with minimal drill smear has prompted much research work in the design of drill bits, drill entry conditions, and drilling spindles.

Drilling is a one-at-a-time process, and punching is a substantially cheaper alternative, especially where this can be combined with profiling, to remove the need for routing. Punching is, however, only practicable when:

Holes are of relatively large size and loose tolerance

Holes are not through-plated, so there is no requirement on wall finish

The production volume is sufficient to absorb the high costs of the tools needed

The laminate material can be punched – for example, those based on woven glass fibre are not suitable.

As the paper-phenolic laminates associated with low-cost applications can be processed in this way, punching is most commonly seen with simple single-sided and double-sided boards.

Double-sided boards are drilled before patterning, so the absolute location of the holes is not important, provided that tooling holes for locating the phototool on the panel are drilled at the same time, and that the relative position of the holes is within tolerance. This means that relatively crude jigging can be used, and allows drilling of a stack of blanks to a depth of approximately five times the drill bit diameter.

Multilayer boards have patterns imaged on the inner layers, and the drilling positions must match these exactly. Three methods can be used to provide accurate hole location:

‘Soft plug tooling’: Tooling holes are pre-punched in the panels, and used first to align the exposure artwork, and then to locate the panel in the drilling machine. The tooling plate on the machine has areas in which replaceable plugs of brass or nylon can be inserted. These are drilled with the actual drill spindle used for drilling the circuit board, to provide exact spindle to tooling location. Tooling pins are then pressed into these holes, and the panels are loaded over these pins.

Post-etch punch registration: Four slots for drill machine positioning are punched, referenced to fiducials on the panel, but taking into account the stretch factors electronically introduced into the laser-plotted phototools. This accommodates the shrinkage (primarily in the warp direction) during the pressing operation.

X-ray registration: Two tooling holes are drilled, precisely referenced to the internal circuit image using X-ray positioning. Panels can then be pinned together and handled as double-sided boards.

Most multilayer boards currently use post-etch punch registration.

Thin sheets of aluminium, aluminium-clad composite or phenolic-paper laminate are placed both on top of and below the stack. The ‘entry material’, 150–500 µm thick, is designed to protect the top panel surface from damage and burrs, centre the bit to prevent deflection, and lower the impact on the bit to minimise breakage; ‘backup material’, 1.6–3.2 mm thick, gives the drill bit ‘somewhere to go’, and minimises burrs on the exit surface. Once used, the sheets will generally be discarded, and may be recycled, depending on the choice of material.

The standard drill for larger holes is made of wear-resistant tungsten carbide crystals cemented in a cobalt binder. However, once drill diameters reduce below 0.5mm, there are problems of drill breakage on removal, and an increase in scrap due to poor hole location. Increasing the percentage of binder makes the drill less likely to break, but more prone to wear and likely to deflect more during drilling. With a standard hard high tungsten carbide content drill, improvements have been reported from using a friction-reducing surface coating of carbon, deposited by chemical vapour deposition (CVD), to produce a diamond-like film.

Drilling can typically account for 20% of the unit cost of a standard multilayer. However, the long-term trend has been towards high density designs with increased use of smaller and smaller via holes, in order to minimise the use of board ‘real estate’. This implies lower stack heights and a resultant significant cost increase.

The practicable limit for drilled holes is around 0.30 mm, below which the drill bits become very fragile. For small vias, etching and plasma techniques are sometimes used, but ‘laser ablation’ is an alternative to drilling that is finding favour, especially for blind vias. Focused laser energy is repeatedly pulsed at the material to be drilled, vaporising layer after layer until a hole is created.

Photoresist and imaging

Terminology to describe phototools is usually ‘positive’ and ‘negative’: on a positive image, the copper features are black and the base laminate features are clear.

The most commonly used photoresists are ‘negative’-working, which means they polymerise on exposure to ultraviolet light and hence become insoluble in a direct developer (Figure 1). Non-polymerised resist is removed by ‘developing’ to expose copper areas ready for electroplating.

Figure 1: The photolithography process sequence

Figure 1: The photolithography process sequence

Volume production of conventional boards usually involves the use of wet etch resists. For higher technology requirements, almost without exception, dry film photoresists are used for outer layers. These resists are normally 35 µm thick and applied using heat and pressure in a laminator (Figure 2). Most dry films are now aqueous processable.

Figure 2: Dry film photoresist – construction and method of application

Figure 2: Dry film photoresist – construction and method of application

The stages of photoprinting

lamination, by applying pressure and heat

exposure: using film artwork which is a negative of the required pattern, exposing the photoresist to ultraviolet light to harden the resist selectively as in the pattern

developing, to remove non-hardened resist

After processing the patterned part (by etching or plating) the remaining (hardened) resist finally needs to be stripped

Inner layer exiting dry-film cut-sheet laminator

Inner layer exiting dry-film cut-sheet laminator

UV exposure machine with ‘glass to glass’ frame

UV exposure machine with ‘glass to glass’ frame

Inner layer exiting dry-film developing machine

Inner layer exiting dry-film developing machine

Inner layer exiting cupric chloride etching machine

Inner layer exiting cupric chloride etching machine

Inner layer exiting dry-film resist stripping machine

Inner layer exiting dry-film resist stripping machine

With correct exposure and developing parameters, resist side walls are almost perfectly vertical and will produce well-defined tracks and spaces. However, this definition can be degraded by poor copper distribution on the outer layer.

Good plating characteristics are crucially dependent on the outer-layer image quality. Imaging must be performed in temperature and humidity controlled clean rooms. A fundamental problem with the flexible photographic films used to generate the images is that their size increases with temperature, typically by 25 ppm/°C. There is also a more complex non-linear response of the film base to humidity. The dimensional stability of the phototool is a critical factor for high precision work. To hold dimensions to one part in 20,000, one needs to hold the temperature to ±1°C and humidity to ±2% RH.

For manufacturers working with narrow tracks and gaps, liquid photoresist is reported to offer a more cost effective method of processing inner layers, in terms of cost reduction, wider process latitude, better adhesion and conformance, and improved resolution. However, the surface of the panel must be free from contamination, and residual particles can also affect the quality of the coating. The photoresist used for this process can be inspected after exposure, because the polymerisation is visible even before development. Inspection at this stage is recommended to increase yield and reduce overall scrap rates.

The photoresist may either be used as the etch resist on its own, or else be used to define the pattern of an electroplated layer of resist, most commonly tin or tin-lead. Outer board layers normally use the latter method.


The main etch processes are cupric chloride and ‘ammoniacal’, the latter using a proprietary blend of chemicals. The choice between the two is influenced by the application – cupric chloride is not compatible with tin-lead used as an etch resist on outer layers, but ammoniacal etchants have a problem with over-etching for fine line circuitry. In order to ensure a uniform etch, both processes are usually applied in a conveyerised, high-pressure spray chamber that exposes the whole board to a controlled, reproducible and constantly refreshed spray of etchant.

Handling without damage is always a challenge for board fabricators: this is a vertical panel stacker

Handling without damage is always a challenge for board fabricators: this is a vertical panel stacker

During the etching process the etchant attacks the copper in a sideways direction as well as down, so the cross-section of the finished trace has a trapezoidal shape: depending on the conditions, the narrowest point may be at the foot, at the top, or somewhere in between (Figure 3). ‘Etch factor’ is defined as the copper thickness, divided by the horizontal distance between the foot and the line edge at the top: the higher the etch factor, the smaller the amount of sideways etch, and the closer the side wall is to being vertical. The chemistry of the bath has a major influence on etch factor, and its oxidation-reduction potential and specific gravity are more important than temperature and spray pressure.

Figure 3: Cross-section of PCB outer layer after etching

Figure 3: Cross-section of PCB outer layer after etching

Shows tin-lead plating overhang on top of a track that has been undercut by etching

Shows tin-lead plating overhang on top of a track that has been undercut by etching

Where impedance control is needed, the trend for thinner inner-layer materials and fine line patterning has impacted on the etching process. Tracks on inner layers must have uniform width across the panel, minimal undercut, and equivalent etching performance on both sides. Process parameters which affect this are free acid concentration and uniformity of spray application.

Line width is fairly difficult to measure, but a good way of assessing average line width is to measure the resistance of a standard trace, which can be monitored using SPC techniques.


Electrolytic plating (‘electroplating’) is a cheap and effective way of building up a layer of copper with almost bulk metal properties. When a direct voltage is applied to two conductors immersed in a solution of a suitable metal salt, current will flow through the solution, and positively charged ions of the metal will be discharged and deposited as a film on the more negative of the two conductors (the ‘cathode’, whence the alternative name of ‘cathodic plating’).

The electrode where electrons enter the solution is termed the ‘cathode’; the one where electrons leave the solution is called the ‘anode’. As electrons are negatively charged, the cathode is rich in negative charge, and the anode is deficient in negative charge. With an applied direct current, ions in the electrolyte tend to move: positively charged ‘cations’ migrate towards the cathode, negatively charged ‘anions’ towards the anode.

Many of the early experiments were carried out by Michael Faraday. His ‘general law of electrolysis’ can be expressed mathematically as the equation:

where W is the weight of substance released, dissolved or deposited; I is the electrode current; T is the time for which that current flows; A is the atomic weight of the substance; Z is the number of electrons involved in the electrode reaction (valency); and F is the Faraday, a constant of value approximately 96,500 coulombs.

The most common type of copper plating solution is based on copper sulphate dissolved in dilute sulphuric acid. The board to be plated is made the cathode of an electrolytic cell, with a piece of copper as the anode. When direct current is applied, copper is deposited from the solution onto the board, and at the same time an equivalent quantity of copper from the anode is dissolved, maintaining the concentration of copper in solution.

The rate of copper build will depend on geometric factors (where the contact is made, whether shadowing occurs, and so on), and electroplated deposits are not necessarily of even thickness, especially with fine lines and down holes. The problem of reduced thickness is particularly acute with:

thicker boards and smaller holes (so-called ‘high aspect ratio’ holes)

boards designed with a maximum copper outer layer to assist with EMC, which preferentially attract electroplated copper to the board surfaces

blind vias – one copper distribution reported was 20 µm in the upper wall, against only 5 µm on the lower part of the wall and on the bottom.

The ability of a solution to plate evenly over a large area (‘covering power’), and to plate into holes (‘throwing power’) depends on the current density, the concentration of acid and copper ions, the agitation of the solution, the anode-to-cathode separation, and the bath additives.

The correct selection of suitable additives is what differentiates suppliers of plating chemicals, so there are many combinations, which are formulated for the intended range of current density. There are usually ‘acid modifiers’ to maintain solution stability, ‘levellers’ to block out high current density areas and encourage deposition on the low current density areas, and ‘brighteners’ to modify the crystal structure and give improved elongation.

Electroless plating

Electroplating needs contact to be made with a fully conductive surface, so can only be used before the board pattern has been etched. Immersion processes (as used for ENIG) work on isolated areas, but this technique can only produce very thin layers. Neither of these processes can create a conductive coating inside a hole: as with a patterned conductor, the hole ‘barrel’ cannot be directly electroplated because the outer conductor tracks are separated by layers of non-conductive laminate.

However, in 1946, scientists experimenting with nickel plating baths, in which a reducing agent was used to inhibit the oxidation of bath constituents, were surprised to find that the amount of metal deposited exceeded that predicted by Faraday’s Law. It was discovered that nickel was being deposited even with no external current, and that plating on a catalytic surface could be brought about by chemical reduction alone. At first, the process was called ‘electrode-less’ plating, but the term ‘electroless’ was soon adopted.

Nickel and copper are the metals most frequently electroless plated, but processes have been developed for tin, tin-lead, cobalt, gold, silver and palladium. One of the advantages of electroless plating is that plating takes place on any activated surface, forming a coating of uniform thickness, and allowing internal surfaces to be plated. The down-side is that the quality of adhesion depends on the nature of the surface, so polished, defect-free surfaces need special chemical preparation before plating.

Electroless copper coverage of PTH

Electroless copper coverage of PTH

Furthermore, the materials are expensive, and the process is fairly slow – ‘high build’ solutions can typically deposit 2.5 µm of copper in 15–30 minutes – so, once an initial thin conductive film has been produced, electroplating is generally used to build up the layer.

Microsection showing relative thickness of underlying foil, copper layers produced by electroless plating and electroplating, and unreflowed tin-lead

Microsection showing relative thickness of underlying foil, copper layers produced by electroless plating and electroplating, and unreflowed tin-lead

The internal metallisation of holes is a critical operation, and the electroless copper process which has been developed includes:

Cleaning and conditioning, to remove imperfections and contamination.

Etching, to create the correct surface condition for good adhesion.

Activation, to create a surface which is strongly reducing in nature. [Nascent hydrogen is often liberated at the surface, and agitation may be needed to ensure that the bubbles produced do not mask areas from exposure to the plating solution].

Electroless copper deposition, using a solution containing a source of copper ions, a reducing agent, and complexers and stabilisers to prevent premature precipitation of copper.

For PTH and multilayer boards, a key stage is ‘de-smear’, to remove any friction-melted resin and debris remaining on the inner copper layers after the drilling operation. This can result in open-circuit vias. Frequently de-smear is accompanied by ‘etch-back’ of the base laminate to expose additional internal conductor surfaces.

De-smearing can be carried out using chemical reagents: chromic acid breaks down bonds, making long polymer chains into short ones, but has health and environmental problems; sulphuric acid actually dissolves the epoxy and is less versatile; the permanganate process is very effective, and methods of regeneration have been developed which prevent the precipitation of manganese dioxide sludge. plasma cleaning is becoming popular as a safe and environmentally friendly dry etching process, able to deal with all laminate types. This uses a plasma – a gas containing positive and negative ions as well as free atoms and radicals – to de-smear and etch back drilled holes. The ‘cold’ plasma used for de-smearing is excited by RF energy, and this is usually done in a vacuum chamber, with a low pressure of a suitable gas.

Direct metallisation

The electroless plating process was developed using formaldehyde. However, this chemical has been classified as a known carcinogen, and can no longer be used without implementing expensive safety precautions including employee monitoring. Anticipating this, plating chemical manufacturers have developed systems with other reducing agents (notably sodium hypophosphite) and a number of alternative ‘direct metallisation’ processes.

An early approach was to use a carbon dispersion to coat board surfaces and hole walls; other systems used graphite, conductive polymers and palladium formulations. Nowadays, a typical process uses a tin-stabilised colloidal palladium dispersion to deposit a film of palladium particles on the surface prior to electrolytic plating. Since this takes place without the evolution of hydrogen gas, holes are more easily accessed and hole walls and vias more evenly plated. The process is complex, involving controlled immersion successively in:

a micro etch, to remove residues from copper surfaces

a cleaner/conditioner, to prepare the laminate surface

a pre-dip, to prevent dilution of the activator

the tin-stabilised colloidal palladium activator itself

an accelerator, to make the palladium deposit less soluble and stabilise the tin

acid, to neutralise alkaline residues and condition the surfaces for electroplating.

One concern is that direct metallisation processes are not selective, and evenly coat all surfaces, requiring post micro-etches and high pressure spray rinsing to strip off unwanted conductive deposits. However, suitable post dip operations can leave the coating only on the dielectric material, and remove conductive material deposited on the foil interconnect, so that copper is electroplated directly on the foil. This gets round the potential with traditional electroless copper processes for ‘inner-layer separation’ (previously referred to as ‘post separation’), where failure occurs either within the electroless copper layer itself, between the electroless copper and the foil, or between the electroless and the electrolytic copper layers.

Section of multilayer junction showing signs of post separation

Section of multilayer junction showing signs of post separation

Lay-up and bonding

For yield protection, it is common practice to use Automated Optical Inspection (AOI) on inner layers before lamination. Then, before the multilayer assembly is laid up for lamination, each internal copper surface is chemically treated in order to promote good adhesion to the prepreg.

One previously common process is referred to either as ‘black oxide’ or ‘brown oxide’. In this, controlled oxidation forms a thin layer of oxide, which both increases the surface area and reduces the reactivity of the copper, passivating the copper surface. The quality of the bond obtained depends on the ratio of cuprous to cupric oxide, and on properties such as the growth rate and porosity of the layer.

When the oxide process has been incorrectly carried out, the panel can be stripped and re-coated. However, the more process cycles, the more possibility of salts or etchant residues after rinsing, which can cause poor lamination or subsequent failure in reflow soldering. There is a marginal effect on copper thickness, as each pass removes 1–2 µm of copper, but this is within the foil thickness tolerance, and should not effect the functionality of even controlled impedance boards.

Probably a preferred alternative to this oxide process is a modified micro-etch. In this, the foil surface remains metallic copper, but its area and roughness are both increased, to enhance adhesion with the prepreg resin.

Prepreg sheets are used between the ‘cores’ to provide both dielectric spacing and adhesion. Prepregs are woven glass fibre mat which has been coated with resin, and dried but not cured (that is, partly polymerised ‘Stage B’ materials). It is normal practice to use two prepregs between layers, choosing from a range of standards to give different bond thicknesses. Special prepregs are used for bonding heat sink to boards. No-flow and low-flow types have been developed which are also used in flex-rigid board manufacture.

Inner layer cores, prepregs and outer layer copper foils are laid-up between press and liner (‘caul’) plates to fill a press ‘daylight’. Standard 1.6 mm thick 4-layer boards would typically be pressed eight-high in one daylight, the board elements being held in correct registration by pinning or equivalent tooling. Liner plates help to give a uniform distribution of heat and pressure.

Bonded panels exiting the cooling press

Bonded panels exiting the cooling press

A conventional hot transfer vacuum press takes around one hour for the hot press cycle, at a temperature of approx. 180°C for FR-4 material. More boards are now being bonded in autoclave presses which have a longer press cycle (3–4 hours) but much greater capacities and flexibility over panel sizes.

One process control used for the lamination process is the glass transition temperature of the panel, although this only measures a composite value for the whole sandwich of previously cured base material and the prepreg which is cured in the press. A small increase in glass transition temperature after lamination gives a good indication that the base material has been fully cured.

Solder finishes

In Board metallisation and finishes, we looked at two main conductor finishes, tin-lead and HASL. With the tin-lead plating traditionally used as an etch resist, there was indeed an obvious option of just reflowing the plating to form a fused tin-lead solder coat. Given environmental pressures to remove lead, with the consequent change to tin plating as an etch resist, this is no longer an option. We are thus left with two main strategies:

To use the HASL process, either with conventional tin-lead solder (at least until this is banned) or a higher melting lead-free equivalent

To strip the tin plating, use electroless nickel to coat the copper metallisation, followed by a very thin coat of immersion gold (the ENIG finish).

Which of these will be chosen will depend on the application – typically ENIG is preferred when fine pitch components are to be assembled, on account of its greater flatness.

The choice of solder finish will affect the detail of the solder mask sequence. Typically solder mask is applied before solder immersion, in order to prevent rippling of the resist on top of reflowing solder during assembly.

Immersion plating

Immersion plating is a simple technique for creating very thin coatings, in which the part to be plated is merely dipped in a suitable metal salt. The top surface layers of the substrate are exchanged with metal ions, causing the metal in solution to plate the substrate surface. A classic demonstration of immersion plating is to put an iron nail into a solution of an acidic copper salt such as copper sulphate: iron is dissolved in the solution, and replaced by copper, covering the nail surface with a thin copper layer.

In order for one metal to immersion plate on to another, the metal in solution must be more ‘noble’, or less readily oxidised, than the substrate. This is why gold can immersion plate onto copper, but copper cannot immersion plate onto gold.

A common immersion plating task is to cover a nickel barrier layer with a (more solderable) thin layer of gold. Process control is helped by the fact that immersion processes are self-limiting. However, the very thin deposits are porous, and migration of nickel or copper from beneath the gold surface after plated boards have been subjected to heat processes will have an adverse effect on solderability and/or wire bonding. [Similar, but more immediate, problems are produced by high levels of nickel or copper in the gold plating solution]

Solder mask application

Early solder mask practice was to print the final image needed by screen printing. This is still the most cost-effective process, and can even be carried out simultaneously on both sides of the board using special printers.

However, most solder mask used in Europe is photoimaged, using either a ‘dry film’ type, laminated to the board in a similar way to photoresist, or a ‘wet film’ type, applied to the board and then dried. Both types then need to be photoimaged, developed and finally cured.

Wet film solder masks can be applied by:

printing through an open screen

‘curtain coating’


Printing requires little equipment, but the wiping action of the squeegee tends to remove resist ink from the leading edge of conductors and skip over narrow spaces between high-density conductors. Ink also tends to build up on the screen around the holes in the board. In order to overcome these problems, screen-coaters will apply two or maybe three layers of resist, and either move the screen between layers or clean or scrape it. Printing liquid solder mask is not a high productivity process!

The curtain coating process was explained schematically in Solder mask. It demands close control of viscosity and conveyor speed, but will give single layers about 25 µm thick over large board or copper areas, with thicknesses as low as 10 µm achievable over fine tracks. The process allows small diameter holes to be coated without the risk of blocking them with ink.

An alternative group of processes involves spraying the resist. As with any spraying procedure, all the techniques involve safety issues and the use of enclosures and extraction.

In electrostatic spraying, droplets of thinned resist are given a negative electrostatic charge, compared to which the earthed board is positive. The process gives a coating that is even in thickness

Conventional pressurised air sprays intermix a thin liquid resin with a small amount of air at the spray gun. Cheaper than electrostatic spraying, the overspray is about the same (10–20%), and the process can also be carried out vertically (as with printing), allowing both sides to be coated before drying.

Solder resist needs final curing in order to reach the necessary degree of permanence. However, once it has been cured, it is very difficult to shift without seriously damaging the board. Prudent fabricators inspect solder resist patterns very carefully before the board is baked. Assemblers will tell you of the times where fiducials are incorrectly read by machines, because they have been partially covered by solder mask, and of problems where stray materials which should have been washed away during development are draped over nearby land areas!

Those who would like to learn more about applying LPISM are recommended to read Shaun Tibbals paper Application methods and their influence on solder mask processing at this link

Adding legend

We talked earlier about printing for applying etch resist to make single-sided boards, and for screening solder mask. The process is also used within the board fab to add legend (also called ‘nomenclature’ or ‘screen print’). None of these fabrication printing processes is anything like a text or graphics application, because we need to apply significant quantities of material, typically in the range 50–150 µm.

In screen printing2, the ‘screen’ employed as an image carrier consists of a rigid frame on which is stretched a mesh (or ‘gauze’) made from fine polyester or stainless steel wires. The mesh acts as a support for a stencil of the required image, which is produced in a photosensitive emulsion applied to the mesh. The mesh support allows total freedom of image design, which can include areas which would otherwise be unsupported – think of a children’s lettering stencil and the webs which need to be left in place in letters such as A and O.

2 The stencil printing process which we use in assembly for depositing solder paste was developed from the screen printing process previously used, in order to be able to print thicker deposits of more viscous material. Because paste patterns are simpler, with no closed areas, the support of a screen is no longer needed, so the mask can be made of etched metal.

Figure 4 shows the starting position of the printer: the screen is fixed just above the board, and the ‘medium’ (ink or glue, for example) lies in front of the flexible squeegee. The mesh of the screen is pushed down into contact with the board by the squeegee as it moves across the screen, rolling the medium in front of it.

Figure 4: Starting position for a screen printer

Figure 4: Starting position for a screen printer

The squeegee blade first presses the medium into the open apertures of the image, and then removes the surplus as it passes across each aperture. The screen then peels away from the printed surface behind the squeegee, leaving the medium that was previously in the mesh aperture deposited on the board beneath (Figure 5). The medium flows slightly immediately after printing to reduce the ‘mesh marks’ left in the print, a process known as ‘levelling’.

Figure 5: The screen printing process

Figure 5: The screen printing process

The process is sometimes referred to as being ‘off-contact’ printing, since the screen only contacts the printed surface at the point where the squeegee passes over it. A typical value for this ‘snap-off distance’ is 0.5 mm for each 100 mm of frame width.

Emulsion is normally applied to both sides of the mesh, and ‘built up’ to a defined thickness on the underside (the side in contact with the board). The total thickness of the emulsion mask and the mesh determines the thickness of material deposited. As a rough rule-of-thumb, the print thickness will be approximately two-thirds of the overall mesh-plus-emulsion thickness.

Most print equipment applies legend just to one side of a board. The ink is then cured, the board inverted, and the process repeated. It is, however, possible to print on both sides at once, using specially designed equipment, but the implication of having wet ink on both sides is that extreme care has to be taken in transferring the board into a suitable curing station.

UV curing of component ident

UV curing of component ident

Note that most of the materials used for legend are high in volatile content, and precautions have to be taken to extract the solvents.

Printing is also used to apply temporary solder mask to selected areas of the board. This resist allows pads and holes to remain unsoldered after wave soldering, and thus available for the manual insertion and soldering of sensitive ‘non-wet’ components. The materials used are designed to withstand immersion in solder without major deterioration, so that they can be removed afterwards. These solder masks are most frequently removed by peeling (‘peelable solder mask’), but other types are designed to be washed away.


Having completed this part of the unit, look at one of the process routes in PCB fabrication sequences, and check that you can identify the key features of each of the main processes.

Compare your answer with the relevant section above