Design for eXcellence

Unit 4: Design for test

Section 3: ICT DfT design issues

Section Contents

In-circuit testing

This section builds on the description of the ICT method in Background to test and inspection, so you may want to revise that material before proceeding.

In-Circuit Test comprises several sections, each consisting of a series of tests on individual devices. By testing devices individually, failures can be determined at the device level, and diagnostics are simplified. The arrangement of the sections grants devices maximum protection from damage due to manufacturing defects. The sections are listed below in order of execution.


Pre-shorts testing allows the test operator to bring the board under test to a known state before the shorts test is run. The operator is prompted to set potentiometers, switches, and jumpers on the board. After all operator actions are complete, the board is ready for the shorts test.

Shorts and opens

These are the equivalent tests to the continuity and insulation resistance tests described above for bare boards. The shorts and opens testing detects unexpected opens and shorts on the board under test. If any are detected, the board fails and no further testing takes place.

The opens test verifies that all expected shorts are present on the board, for example, jumpers and inductors. A resistance measurement is made between a pair of nodes that are expected to be shorted. If the resistance is less than or equal to a threshold value (a short), the test passes. If the resistance is greater than the threshold (an open), the test fails.

The shorts test detects unwanted shorts. The shorts test consists of two phases: a detection phase and an isolation phase. During the detection phase, each node is tested for unexpected continuity to all other nodes. If a measured resistance is less than or equal to a defined threshold (a short), the isolation phase is executed to determine which of the nodes under consideration is shorted to the node being tested. Shorts and opens thresholds are determined from the circuit description and are set individually for each node.

Unpowered analogue

Unpowered analogue testing verifies the values of individual components on the board under test. The tests are performed with the board in an unpowered state. Each Unpowered analogue test can fit into one of two general categories:

  1. Constant AC/DC voltage test – A known voltage is applied across the component under test and the resulting current flow through the device is measured. This method is used for testing passive, linear components such as resistors, capacitors, and inductors.

  2. Constant current test – A known current is applied through the component under test and the resulting voltage across the device is measured. This method is used for testing passive, non-linear components such as conventional diodes, Zener diodes, and transistor PN junctions.

Eliminating the effect of parallel impedances is a crucial part of unpowered analogue testing. Direct and indirect parallel impedances from other components on the board tend to introduce a significant error. A method known as guarding may be used to eliminate some of the parallel impedances. However, not all parallel impedance paths can be eliminated in all situations.

Unpowered vectorless

Unpowered vectorless testing is designed to locate device pins that are not properly soldered to the board and polarised capacitors that have been installed with the wrong orientation. These tests are performed without power to the board.

Unpowered vectorless testing is typically used to test SMT connectors, complex devices without test patterns, and complex devices requiring a short test lead-time. This technique can also verify the orientation of polarised capacitors whereas the standard analogue measurement cannot. The ability to accurately detect capacitor polarity relies heavily on the size, package and physical orientation of the capacitor. Tantalum and aluminium surface mount capacitors or axial lead capacitors can be checked for polarity orientation as long as a plate can be mounted over the top of the capacitor. Large value capacitors and capacitors in parallel with many other capacitors may not be testable using this technique, but the value of the capacitor can still be checked during unpowered analogue testing.

Capacitively coupled

A plate mounted in parallel to the device under test (DUT) is placed so that it is as close to the device as possible. An AC source is applied to the individual pins of the device that creates an electromagnetic field between the device pins and the plate. Field strength is measured as a voltage and if the received voltage is greater than or equal to the specified threshold, the pin passes. If the voltage is less than the specified threshold, the pin will fail. This test simply verifies continuity between the DUT and the PCB. If more than one pin of a device is connected to the same net, this testing technique does not verify that all the pins are making contact with the net. It only verifies that at least a single pin is connected to the net. For this reason, multiple ground and power pins on a single device package cannot all be tested individually for continuity to power and ground.

Diode drop

Ground pins cannot be tested using this technique. All other pins are tested for a diode drop to ground. The pins are tested by applying an AC source at different thresholds and frequencies and reading the resulting voltages on other pins of the device (detector pins). The detector pins may be DC biased to allow a stronger signal to propagate through the device. The test limits are learned using a software algorithm and a known-good sample board. Test coverage using this technique can only be assessed after the test program is in place.

Controlled power-up

Once the pre-shorts, shorts and opens, unpowered analogue, and unpowered vectorless tests have been completed, the controlled power-up test is performed. Power is applied to the board at the specified voltages while supply currents are closely monitored. If the board draws more current than the board specification allows, the power supplies are immediately shut down and the test fails. The intent is to avoid damage to the components on the board from defects not found during previous tests. Such defects include reversed polarity of electrolytic or tantalum capacitors, incorrect orientation of integrated circuits, and other similar problems.


For very large circuits, internal circuits are often provided which assist the ATE to perform the tests. The best known is Level Sensitive Scan Design (LSSD) or ‘internal scan’. Internal scan (full, almost-full or partial) is used to separate combinational from sequential circuitry and to break internal feedback loops to facilitate ATPG. It also provides excellent circuit portioning, control and observability. At assembly level the best-known approach is ‘boundary scan’, JTAG or IEEE 1149.1.

A boundary scan circuit receives test instructions from the ATE and performs logical tests on the interconnects between the digital circuits that it controls. This capability is important for large IC packages containing many connections, particularly if the ATE cannot otherwise access them for test. Boundary scan can also be used to test some on-chip functions. The international standard for the boundary scan approach is IEEE 1149.1. Most modern digital ICs include boundary scan capabilities, and it is important to include them in ASIC design to facilitate board or other assembly level testing.

Figure 1: Internal representation of an IC with boundary scan capabilities

Internal representation of an IC with boundary scan capabilities

Boundary-scan relies on special architectural features built into IC’s. The key feature is the insertion of a boundary-scan cell between each pin and the chip circuitry to which that pin normally is directly connected (Figure 1). These cells are also interconnected serially to each other so that they form a shift-register path around the periphery of the IC. Data can then be shifted in and out of the boundary scan cells serially through the test access port (TAP). To test boundary-scan devices, access to the TAP is required. Also, the boundary-scan device must be described using the boundary-scan descriptive language (BSDL) and comply with the IEEE standard 1149.1.


Digital testing attempts to isolate and test each digital device individually. This allows for maximum diagnostic capabilities with minimum customisation of tests for different boards.

These tests are designed to verify that the correct device is loaded on the board, is oriented and functioning correctly, and has all pins properly soldered. Inputs are supplied to each device using drivers that have adjustable voltage and timing settings. Outputs of the DUT are connected to programmable receivers and are verified against expected results. Less complicated devices are usually fully tested and all internal logic functions are exercised. However, complex devices, such as microprocessors, are fully tested for pin function, but not for full logic function.

To isolate digital devices, all the surrounding devices are disabled. Disabling is the process of placing the device pins on a particular node into a high-impedance state - except for the pins of the particular device being tested. When this is accomplished, the tester has the ability to drive and receive on a node without contention from other devices. In cases where it isn’t possible to disable all the other devices on a node, the outputs on the surrounding devices connected to inputs on the DUT must be back-driven.

Self Assessment Questions

What does it mean when components are back-driven? What are the problems and how would you overcome them?

Compare your answer with this one.

Powered analogue

Analogue devices like op amps, voltage regulators and oscillators are tested with power applied to the board. AC and DC voltage sources are used to stimulate the device, and AC and DC detectors are used to verify the response of the device.

As with digital testing, analogue devices must be isolated by disabling other connected devices. Disabling allows stable, repeatable analogue measurements to be taken on the DUT. When disabling methods are not available, back-driving may be used to overcome device contention. Back-driving is not recommended as an alternative to placing device pins into a high-impedance state because of the risk of device damage.

Digital and analogue mixed

Devices such as analogue to digital converters and digital to analogue converters require a mixed test method. In mixed testing, digital drivers and receivers are used on the digital pins of the device and analogue sources and detectors are used on the analogue pins.

Disabling devices connected to the DUT is very important for mixed testing, as the time required to set up and run a mixed test is typically much greater than for digital or powered analogue tests.

Powered functional

Situations arise where it is advantageous to test a portion of the board as a functional cluster. A functional cluster is a group of components that are configured to perform a definable and testable function. Examples include analogue filters and amplifier circuits.

Functional testing may also be necessary due to a lack of full nodal access to the board. In this case, accessible inputs are stimulated, and circuit response is verified on accessible outputs.

The disadvantage of powered functional testing is the loss of diagnostic capability. If a functional block fails, it isn’t possible to accurately determine which particular device caused the failure.

The greatest advantage of powered functional testing is in using it as an addition to a full in-circuit test. The advantage of device level diagnostics is retained while also verifying that groups of components work together as designed.

Board level functional

Some kinds of board level functional tests can be run on the ICT. These differ from powered functional tests in that a dual-level fixture is used to disconnect the board from probes used for ICT. Only probes used for the functional tests remain in contact with the board, thus reducing noise and loading.

Board level functional test relies on instruments within the ICT along with external instruments such as oscilloscopes, frequency counters, high-voltage supplies, and RF sources. A detailed functional test specification is required and not all functional test requirements are possible on the in-circuit tester.

ICT fixtures

The connection between the ICT and the unit under test (UUT) is made through a test fixture called a ‘Bed of Nails’. The nails (see Figure 2) are spring loaded probes that make contact with the test point (unmasked vias, THT components, test pads, and gold fingers). The reliability of the contact is directly related to the fixture type, size of the UUT, size of the contact targets, target registration, and the placement of the targets.

Figure 2: A detailed view of a spring-loaded probe in a test nail

A detailed view of a spring-loaded probe in a test nail

Bare board test fixtures

Test points for BBT are the lands of components and a fixture is usually universal where the flexible probe position is adjusted through alignment plates. Custom fixtures are also possible.

Universal fixtures

Figure 3: Universal test fixture showing flexible probes and translator plates guiding probes

Universal test fixture showing flexible probes and translator plates guiding probes

This gets its name from the fact that the probe pin ends that go into the tester mate into a fixed size grid of contact points and consequently one fixture can be used for many boards. Most universal fixtures are on 2.5 mm (100 thou) grids and an example is shown in Figure 3.

Probe points can be anywhere on a board and are not usually in a grid layout. To get around this problem flexible probes are used. They are angled to the correct points as in Figure 3. To make the fixture three plates are drilled to support and bend the pin to the probe point on the board.

In a 2.5 mm grid the density of pins is limited to approximately a 5 × 5 matrix or 25 pins per cm2. This poses a problem for designs with high lead count fine pitch or densely spaced components. Angled probes would be used to gain tighter spacings and increase the pin density but where this isn’t possible a custom fixture will be required.

Custom fixtures

Each board has a fixture built for its test process including test head and plates. These fixtures have the advantage of coping with high probe densities but are more expensive and at present there aren’t many bare board test systems available that will accept them.

Single-sided boards

Figure 4: Single-sided test fixture

Single-sided test fixture

The single sided fixture for bare board is designed to probe the component side. This side must be tested because it contains both the leaded pads and SMT lands to be probed. A vacuum is used to force pin contact to the board and tooling holes are necessary for accuracy registration with the fixture. These will be discussed later in the section on board design issues.

Double-sided boards

Where components have been designed on both sides of the PCB double-sided probing is available. There are three options:

  1. Double-pass testing This uses the single-sided probing twice but with different fixtures for each side. Testing one side only causes problems for the board’s vias and leaded components.

  2. Via-only testing Strictly speaking this is not double-sided because the equipment only probes THT leads and vias on the bottom-side of the board. This reduces the testability of the board and is not usually recommended.

  3. Double-sided clam shell fixture This provides 100% testing of the board because all the lands and pads are probed simultaneously and all routing and plated through holes are checked. Figure 5 and Figure 6 show diagrams of the double-sided clamshell fixture.

Figure 5: Double side bare board testing

Double side bare board testing


Figure 6: Double-sided clamshell fixture

Double-sided clamshell fixture


Figure 7 shows some of the common probe types used for BBT.

The spear probe is used for probing pads where solder mask residue may be present. It has a fine point that could leave a mark after probing. Some companies use this as a check for probing.

The blunt tip probe avoids the piercing of fragile lands and has more contact area that improves probing accuracy.

The pyramid head probe is used to probe plated through-holes. It comes in 3 and 6-sided varieties.

Probe diameters are typically 0.25 mm (10 thou) larger than the finished hole and can be between 30 mm and 100 mm long.

Figure 7: Common probe types for BBT

Common probe types for BBT

Assembly test fixture

The fixture for assembly ICT is similar to BBT but different test equipment and fixtures are used. Test points are test pads, THT pins and vias. In BBT, the Universal fixture has a universal test head and several alignment plates are used to direct the probe to the test point. In contrast, the assembly fixture is custom built and has the pins mounted in two plates and wired to the test head of the test system. The most common fixture style is the single sided fixture as in Figure 8. The double-sided clamshell fixture is the same layout as the BBT clamshell in Figure 6.

Figure 8: Single-sided ICT test fixture

Single-sided ICT test fixture

Probe types

Figure 9 shows the common probe types. Assembly probes are chosen in the same way BBT has different probes for different uses. The serrated tip is used for non-via pads or plated via pads. The crown tip probe is used on components because it twists as it is compressed, creating a scrubbing action that makes a good contact through flux or oxides on the tip, although this can cause surface damage to copper on a board. The spear tip probe is less commonly used now because it can slip off the probe pad, pierce pads and is susceptible to damage.

Figure 9: Common probe types for testing assemblies

Common probe types for testing assemblies

Requirements of a test fixture manufacturer

In order to provide a PCB test application (program and fixture) test fixture manufacturers require certain items, the deliverables, which must be of the latest revision. Incorrect or out of date deliverables will cause extra debug time and possibly extra time on the client’s site. The following list clarifies what is needed and why.

Fixture cost considerations

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Board design issues

DfT checklist

A simple DfT checklist could be something like the following:

On the other hand, Agilent have produced a DfX scorecard that includes a DfT section (Figure 10). Each issue is rated between 1 and 9, 9 being the most desirable. For example, test pad size and separation are both included (A21 and A22) with the largest values scoring 9 and the scores reducing as the values reduce.

The Agilent DfX engineer averages each set and takes the product of the four averages of checklists for a DfX rating. If the rating exceeds a certain level, the DfX engineer returns the design to the designer with recommendations for redesign.

Figure 10: The DfT section of the Agilent DfX scorecard

The DfT section of the Agilent DfX scorecard

General design issues

Test points

The design layout should provide a test point for every net node of the circuit, including unused IC leads. A test point refers to any feature that is probed during electrical test (for example a test pad, untented via or THT lead). A test pad is a solid area of exposed metallisation (usually a 1 mm or 40 thou diameter pad) and there is no through hole. The test probe strikes the flat surface of the test pad. An untented test via is a plated through hole with an exposed annular ring and the test probe strikes either the solder that fills the via during processing (the via barrel) or the pad itself.

Activity: Using vias as test points

Vias can be used as test pads for BBT or ICT. This seems like a good option because it saves design time and board space. There are also problems. Can you think what they might be?

Compare your answer with this one.

Here are some general points to adhere to when designing a board with test points:

Figure 11: Bare-board test pads added to fine pitch pads

Bare-board test pads added to fine pitch pads


Smaller boards are often panellised for more efficient board fabrication and assembly. Usually the images are depanellised before electrical test. This means each image requires tooling holes.

Tooling holes

There are two reasons for including tooling holes when incorporating DfT:

  1. For aligning the bare board fixture during testing. Tooling holes will be included in the assembly panel because the panel will be tested after removal from the fabrication panel.

  2. For aligning the assembled board during testing. Each image in the panel requires tooling holes because each board will be tested individually.

The location of the holes is important and also the area around the holes must be free of board features. The holes are typically located near the corners of the board approximately 5 mm (200 thou) or more from the edge. The holes are unplated because the plating process introduces wider tolerances to the hole. Plated holes are used when a tolerance of 25 µm (1 thou) or less can be guaranteed. Gasketing around the tooling holes dictates the nearest test point. Ideally, there shouldn’t be any test points closer than 6.25 mm (250 thou) to the holes. Figure 12 shows a daughter card with unplated tooling holes in the top left and right corner of the board. The four plated through-holes are used to mount the card to the main board.

Figure 12: A PCB assembly showing tooling holes in the two top corners, Agilent Technologies

A PCB assembly showing tooling holes in the two top corners

Specific design issues

The most important influence of DfT on a board design is the method of electrical test. The two methods described in this document are ICT and flying probe testers. The DfT guidelines will depend on which is used. What follows is a discussion of the specific design guidelines for ICT and flying probe testers. It is interesting to compare the two as each can suggest opposing design guidelines.


For ICT, there are some general design considerations:

Figure 13: Diagram of larger components in routed fixture

Diagram of larger components in routed fixture

Flying probe testers

Flying probes are often used when full access is not available due to space availability, performance considerations, or when DfT rules have not been implemented.

Some general points to remember are:

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Test decisions and test economics

Engineers are constantly faced with compromise, and the test process is no exception. Part of the test engineer’s job description is making sure the board and assembly can be tested thoroughly, efficiently and cost effectively. Decisions made when designing the test process will be based on the following:

Costing a test process

A simplified cost process is presented in Chapter 10 of Test Engineering by Patrick O’Connor and is reproduced here. Figure 14 shows a typical arrangement for manufacturing inspection and test flow of a PCB. In this case AOI is the first inspection after assembly; this is followed by ICT, then Functional Test. All units that pass move on to the following stages and are eventually shipped. Units that fail move to the diagnosis and repair station after which they are resubmitted to the MDA. The proportion of each station that fails is d.

A simple model for the manufacturing and test cost per unit is:

C = CA + CI + CM + CF + ( CR + CM + CF )( di + dm + df )

Figure 14: Test flow for an electronic assembly

Test flow for an electronic assembly

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Test coverage

In a test process the function of the ATE is to:

The probabilities of these being performed properly are called the ‘test coverage’. There are nearly always some types of faults that the ATE will not be able to detect or diagnose, particularly if test time is limited, so coverage will never be 100%. DfT is used to ensure coverage of 95–98% for modern boards (50–80% for poorly designed boards).

Table 1, Table 2 and Table 3 are taken from an example provided by Agilent. It represents their opinion of the amount of coverage each test and inspection method will give. More importantly it also shows the coverage from a combination of the methods. The faults are shown on the left hand side, test equipment along the top and the coloured boxes represent yes/possible/no test for fault for green/blue/ red respectively. Notice for example, how difficult it is to pick up a misaligned (but still soldered) part unless a technique like X-ray is used. This leads on to the final three columns in Table 3. This is the predicted test coverage using a combination of tests.

Table 1: Agilent’s view of the coverage of some test methods
Agilent’s view of the coverage of some test methods


Table 2: Agilent’s view of the coverage of some test methods
Agilent’s view of the coverage of some test methods


Table 3: Agilent’s view of the coverage of some test methods
Agilent’s view of the coverage of some test methods

Complementary and overlapping fault coverage

Different factors constrain test strategies on boards that serve different marketplace requirements. Sometimes the constraining factor is access, in which case the software can be used to deliver a complementary test approach between ICT and X-ray, for example. This complementary test approach could be executed in two ways, the software should support both and the preferred approach depends on business requirements:

  1. Maximum X-ray complemented with simplified ICT This strategy achieves maximum probe and test pad reduction because it assumes that shorts and opens will be tested on each and every pin at X-ray, and furthermore that overlapping shorts/opens coverage on these same pins is not required at ICT. With this methodology, ICT is used only to verify that a functional part of the correct value has been placed at the location with the correct orientation. This can be achieved by testing only one unit of a multi-unit analogue or digital device. This is one example of a complementary test approach where the test methods are used in a manner to minimise their fault coverage overlap and achieve maximum probe reduction (3 probes vs. 12 in this example). DfT software can be used early in the design cycle to deliver a test plan that minimises the requirement for test pads and fixture probe count, thereby reducing fixture cost, complexity, weight, debug time and lead-time – a desirable strategy for boards with limited access and in manufacturing environments that struggle with fixture repeatability issues on high probe count boards.

  2. Maximum ICT complemented with simplified X-ray On the other hand, other manufacturers may want to pursue strategies with maximum ICT on boards with limited access followed by selective X-ray to fill the test coverage gaps at ICT due to loss of access. Since ICT is generally a much faster test method than X-ray, manufacturers with very high volume requirements might prefer this technique to the first. The software could be used to prioritise access requirements for designers prior to the layout routing stage of PCB design in order to selectively place test pads where they add the most test coverage. X-ray could be used to only provide coverage where ICT does not have coverage, thereby minimising the X-ray test time.

Other types of assemblies like airbag or avionics boards that are destined for high reliability applications often require overlapping test coverage to minimise the possibility of defect escapes. Understanding that no test method is perfect, some assemblers prefer a high level of overlapping fault coverage to ensure all possible defect opportunities are sufficiently screened. Effective DfT software should enable users to pursue both complementary and overlapping test strategies and to identify the degree of fault coverage overlap in their test plan to meet the quality and reliability requirements of the end use environment. Test strategies more focused on complementary coverage will tend to deliver higher throughput and lower cost than overlapping test strategies that verify the same fault types at multiple stages. The optimum test strategy depends on the end use application and user requirements for test access, throughput, cost, and reliability. Effective DfT software can help manufacturers understand, quantify and analyse these factors in order to strike a balance that is appropriate for the particular assembly and their manufacturing business objectives.

SAQ: Comparison of test methods

Table 4 below has a list of factors along the top row and the common test methods down the left hand column. Can you fill in the table showing the cost of running the test system, the development cost of the test programmes, the speed of the method and the types of faults detected and missed for each method? For costs and speed, the categories high/fast, medium and low/slow will be sufficient.

Table 4: Matrix of test processes and their respective strengths and weaknesses
test method/approach cost programme development test speed faults detected faults missed
manual vision
boundary scan

Compare your answer with this one.

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