Design for eXcellence

Unit 2: Design for fabrication

Section 2: DfF – panelisation and build

Section Contents


The cost of a panel is made up of 40% materials, 20% process materials, and 40% overheads and labour. Using the panel as effectively as possible becomes very important, because you pay for the whole of the panel even if you only use half of it, and only minor savings (for example in drilling and profiling time) can be made. So you incur all the costs of materials and process materials, and most of the labour/overheads.

A typical range of standard panels1 available is given in Table 1:

Table 1: Standard panel sizes available
inches mm routed down or double-sided
24 x 14
609.6 x 355.6
605 x 351
24 x 18
609.6 x 457.2
6.5 x 453
24 x 20
609.6 x 508
605 x 504
24 x 21
609.6 x 533.4
605 x 524
24.4 x 14
619.76 x 355.6
615 x 351
24.4 x 21
619.76 x 533.4
615 x 524
25.2 x 14*
640 x 355.6*
635 x 351*
25.2 x 21*
640 x 533.4*
635 x 524*
625 x 510**
* Only use after consultation
** Double-sided only

1 All the specific figures on this page are based on the Circatex Capability Statement as at December 2002. They are representative of general practice within the industry, but you should always check with your supplier before deciding on a board specification.

To get the best utilisation factor, take your circuit board element, and try laying it out on panels of different sizes, with the circuit stepped both vertically and horizontally. The best usage might in fact be a combination of vertical and horizontal alignment (Figure 1). In doing this you should also take account of how the board will be handled by your assembly house, and look for an overall lowest cost solution.

Figure 1: An example of sub-optimal panelisation

An example of sub-optimal panelisation

In order to understand how best to lay out your circuit within the panel, you need to know what margins to leave. Typically the fabricator requires a no-go border of between 15 mm and 25 mm within the outline of the panel to facilitate handling and to accommodate various features such as identification, fixturing, registration and location tooling associated with his manufacturing process. You will see from Table 2 that, for this particular fabricator, the margins required are different for the four sides, for a range of process reasons2, and there are further requirements for multilayer products, again dictated by the tooling.


Table 2: Margins required for double-sided product
margin between circuit and reason for margin
photomech resist placement plating rail rout LPISM
bottom of panel
top of panel
left of panel
right of panel

As a designer, you will find it difficult to deal with this level of detail, especially as panelisation is an area where you must expect differences between fabricators .There are two ways of approaching the problem, both of which will involve consultation with board production:

Either way, you need to check your design if it looks close to the limit and seek advice about where to position your design and what separation to allow between sub-panels. Note that, overall, the useable area is substantially smaller than the original panel.

Table 3: Useable area – double-sided
routed down useable area
605 x 351
564 x 323.8
605 x 453
564 x 425.8
605 x 504
564 x 476.8
605 x 524
564 x 496.8
615 x 351
574 x 323.8
615 x 524
574 x 323.8
635 x 351*
594 x 323.8*
635 x 524*
594 x 496.8*
625 x 510**
584 x 482.8**
*Only use after consultation
Double-sided only

There is a massive savings potential in correct panelisation. Maybe shaving only 5 mm off one dimension for your product will halve the cost of the board. But of course you can only achieve this saving if you thought about it early enough in the day to be able to adjust the rest of your design, which may include the packaging of the board within its housing.

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You will always be encouraged to use available standard materials and the standard thickness tolerance of ±10%. For two-layer boards, the range of available nominal thicknesses (including copper) would typically be:

0.5 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.6 mm, 2.0 mm, 2.4 mm, 3.2 mm

Of these, 1.6 mm is still the most common, being close to the earliest “one-sixteenth inch” board practice for which many connectors were designed.

Multilayer builds are a totally different affair, and a major cause of both holds and additional cost. In the past, there have been ‘standard builds’, but now they may differ greatly. In fact it has even been said that there is “no such thing as a standard”.

The key information that the fabricator needs is the required eventual thickness. This is because the final pressed thickness depends not only on the starting thickness of the materials, but also on the percentage coverage of copper, the resin flowing to take the place of copper removed by etching. This is referred to as the ‘pressed-out loss’.

Figure 2: The source of pressed-out losses

The source of pressed-out losses

Given the percentage coverage on each layer, and the fruits of experience, one can generate a spreadsheet with macros that enables you to calculate the likely pressed thickness of the board. Some programmes will also indicate the likely shrinkage of the layers, and give information on dielectric properties for controlled impedance boards.

Self Assessment Questions

  1. Describe the process you would go through to panellise a double-sided product.

  2. Describe the source of pressed-out losses.

compare your answer with this one

One of the most common issues that cause confusion between the PCB fabricator and his customer is where the thickness dimension is to be applied. Often the drawing is ambiguous and therefore the most important factor is to specify where the measurement is to be taken. Figure 3 shows the choices available.

Figure 3: Possible choices for board thickness dimensioning

Possible choices for board thickness dimensioning

The following rules are suggested for multilayer builds:

Symmetrical and balanced build

Unless absolutely necessary for electrical reasons the board should be designed symmetrically around the Z-axis. The result of bad balancing of the Z-axis will be excessive warp, and twist. Figure 4 shows two boards: a ‘good’ board on the left and a ‘poor’ board on the right. The poor board has a variation of core and copper thickness resulting in asymmetry.

Figure 4: A ‘good’ board with a balanced stack up and a ‘bad’ board with an unbalanced stack up

A ‘good’ board with a balanced stack up and a ‘bad’ board with an unbalanced stack up

An unbalanced copper weight on the cores will make the etching process expensive. In Figure 5 we can see four examples of a 10-layer board. The worst board on the right-hand side has different copper weights on three of the cores and is not symmetrical about the centre line. The bad example has equal copper weighting on each core but still has asymmetry about the centre line. The OK example shows a symmetrical board and each core is balanced but there are different copper weights used throughout the board. The best example has the same copper weight throughout the entire board and is the most desirable option.

Figure 5: Four 10-layer boards with different build options

Four 10-layer boards with different build options

Whenever possible select the same copper foil weight throughout the build, but if different copper weights must be used (for example, 35 µm for signal layers and 70 µm for power/ground layers) then try to use the same copper weight on each core


Historically, two layers of prepreg have been used to separate foils and inner layers, on the principle that one is unlikely to get glass cloth flaws in successive layers, so the yield would be better. With improvements in the quality of the glass cloth used for prepreg, and the use of ‘resin rich’ prepregs, with a higher percentage of resin, it is possible to create reliable assemblies with just one layer of prepreg (Figure 6). The cost saving can be quite significant in terms of both material and handling, with a six-layer 1.6 mm build comprising just seven components rather than ten. Again, this is not a view that every fabricator will hold, which is why you need to select your fabricator and then agree a process for minimum cost.

Figure 6: Single prepreg builds for 4, 6 and 8-layer boards

Single prepreg builds for 4, 6 and 8-layer boards

Dielectric spacing

The minimum dielectric may be specified, if required, but individual spacing between copper layers should be left to the fabrication house, unless electrical requirements dictate that it be controlled.

Figure 7: Build and cost implications of specifying dielectric thickness

Build and cost implications of specifying dielectric thickness

The above example shows that three additional plies of prepreg would be required for the design on the right-hand side. This could add 10–15% to the cost of the board.


A good rule of thumb for thickness tolerance is to use ±10%. If a particular pair of copper layers requires a tighter tolerance, specify it on those layers only. To maintain tighter than 10% tolerance the fabricator must use higher glass to resin ratio in the build and this generally increases cost. The other option is to sort at final and eliminate the out-of-specification product. Again, the customer will pay a premium for the sorting as well as the fallout.

Layer count

“The lower the layer count the lower the cost”. This is almost always the case, but not always! An 8-layer design with 150 µm lines, and via holes 250 µm or larger, may well be cheaper to manufacture than a 6-layer with 100 µm lines and 150 µm vias. There is no direct formula to follow but the designer must be aware of the capabilities of the fabricator he intends to use, both prototype and volume. In almost all cases an even number of layers should be used. A 5-layer PCB is no less expensive to fabricate than a 6-layer and may have some significant manufacturability issues due to warp and twist.

Self Assessment Question

When designing a PCB, the fabricators will state a preference for a balanced and symmetrical board. Describe what this means, and why this benefits the fabrication process.

compare your answer with this one

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