Design for eXcellence

Unit 2: Design for fabrication

Section 3: DfF – drilling and copper layers


Section Contents


Drilling

Aspect ratio

The key aspects of drilling design, shown by the contrast between cost effective designs and ‘technical’ designs, is the aspect ratio. This is in general the ratio of the depth of a hole to its width, and a fabricator will define the aspect ratio as the ratio of board thickness to hole diameter (Figure 1).

Figure 1: One definition of the aspect ratio of a hole

One definition of the aspect ratio of a hole

There are differences in practice of which you should be aware:

However measured, aspect ratio is a major factor in yields through plating process, with a high aspect ratio leading to plating ‘voids’ that are not detectable until bare board test. This gets particularly difficult when the holes are small.

In consequence, a typical capability statement1 will have different categories for aspect ratio depending on the hole size (Table 1).

1 Unless otherwise stated, all the specific figures on this page are based on the Circatex Capability Statement as at December 2002. They are representative of general practice within the industry, but you should always check with your supplier before deciding on a board specification.

Table 1: Aspect ratio as a function of hole diameter in relationship to capability statement
volume capability
hole size no review DfF review pilot/special
0.25 mm
6 : 1
8 : 1
10 : 1
<0.4 mm
7 : 1
11 : 1
panel thickness dictated
³0.4 mm
7 : 1
12 : 1

An alternative approach to recommending aspect ratio limits is shown in Table 2. Here the minimum suggested drilled hole diameter is expressed as a function of the board thickness, and does not reduce in line with the board thickness, the minimum hole size being determined by the fluid dynamics of the plating processes.

Table 2: Drilled hole aspect ratio chart (Merlin Circuit Technology)
start board thickness drilled hole diameter aspect ratio
0.5 mm
0.20 mm
2.5 : 1
0.5 mm
0.25 mm
2 : 1
0.8 mm
0.25 mm
3.2 : 1
1.6 mm
0.30 mm
5.33 : 1
2.4 mm
0.30 mm
8 : 1
3.2 mm
0.30 mm
10.7 : 1
4.0 mm
0.50 mm
8 : 1
5.0 mm
0.50 mm
10 : 1

Note that the hole diameters given do not represent the technical limit, but rather what can be achieved at 100% yield, with DC plating and no special process conditions. Smaller holes would be achieved by such means as better aeration of the plating bath, vibration to prevent bubble formation in small vias, and pulse plating.

Hole sizes

Most PCB fabricators have a wide selection of drill (hole) sizes available. Some charge per drill size used, others offer a standard set of drill sizes for no charge and then charge for any non-standard drill sizes.

When choosing a hole size to fit a component lead, remember that the internal plating will reduce the effective diameter of the hole. Plating thicknesses vary considerably, but are likely to be in the range 25–75 µm.

As with aspect ratios, the capability statement will categorize different hole sizes (Table 3). Note that capability statements for other fabricators will use slightly different terminology. For example, the ‘volume capability – no review’ column may be described as ‘cost effective design’, whereas the ‘pilot/special’ column is regarded as ‘technical design’.

Table 3: Drilling design categories
dimension volume capability pilot/special
no review DfF review
minimum drilled hole size
0.30 mm
0.25 mm
0.20 mm
non-PTH size
±25 µm
<±25 µm
drill-to-drill tolerance
±50 µm
<±50 µm
controlled depth datum top
±150 µm
<±150 µm
datum bottom
±100 µm
<±100 µm
nail-head ½ oz
200%
170%
1 oz
150%
135%
2 oz
135%
125%
hole roughness
35 µm
<35 µm
countersunk holes
yes
counter-bored holes
yes
second drill tolerance
±200 µm
±150 µm
±100 µm

Pad sizes

The biggest issues to do with pad size are solderability and manufacturability. Solderability is a matter of process and materials control and will not be considered here as it lies within the remit of our Materials and Processes for EDR module; manufacturability is concerned with whether or not the pad will be broken when the hole is drilled in it.

Figure 2: Minimum annular ring 2

Minimum annular ring

2 The photograph actually shows a problem caused by poor outer-layer photomechanical alignment, rather than drilling positional accuracy, but the end result is the same – whether or not an annular ring is visible will be a function of relative pad/drill sizes coupled to positional accuracy.

This is mainly a function of the accuracy of the fabricator’s drilling process. Don’t forget that, for reasons of economy, drilling is carried out on a stack of boards rather than one board at a time. As well as targeting errors, deviations from intended position can therefore be caused by misalignment between boards, and the fact that drills tend to ‘wander’ as they go through the stack.

If a drill hole is slightly off-centre (‘misregistration’) the pad may be broken at one edge, possibly leading to an open in the circuit (‘tangency’ or ‘breakout’). A standard requirement for pad sizes is a 125 µm annulus. For example, a 0.7 mm diameter hole would require a 0.95 mm pad. However, something a little larger than this, maybe a 250 µm annulus, is recommended for soldering, and the CECC 23000 recommendation is that the outer pad diameter should be 0.5 mm greater in diameter than the nominal finished hole size, in order to ensure 80 µm minimum copper annular ring.

Sometimes it is not possible to increase the annular ring without breaking other manufacturability rules. A good second option is the addition of ‘teardrops’ to via holes where the track enters the pad (see Figure 2). This modification usually does not require major change to the design and adds a factor of safety to the annular ring. This feature can be added at layout or by the fabricator. A typical design would add a pad 250 µm greater than the via finished size and position it 250 µm along the track.

Figure 3: Annular ring problem and possible solutions

Annular ring problem and possible solutions

The final option is to relax the specification, allowing drill breakout along one-quarter of the hole perimeter (referred to as ‘90° breakout’), and this is permissible for some consumer applications.

Hole density and clearance

Hole density is purely a cost issue. The more holes there are on a board, the longer the drilling process will take, the more drills will be used, and the more wear and tear there will be on the equipment, so the more the board will cost. Also, as hole density increases, so does the chance that the board will be defective: most fabricators set a maximum hole density and boards with greater density are charged more pro rata.

Whenever possible non-plated holes should have adequate clearance around them on both sides of the board. Circatex recommend a minimum of 305 µm free of metal (Figure 4): this allows both non-plated and plated holes to be drilled during the same operation, which is required to maintain good registration between the two types of holes. Other fabricators recommend 0.5 mm clearance between non-plated through-holes and adjacent pads or tracks.

Figure 4: Annular ring: requirements for tangency

Annular ring: requirements for tangency

Note that, if copper is required to be nearer the hole than the minimum recommended clearance, non-plated through-holes must be drilled after the plating operation, using a separate set-up. This demands tight positional tolerancing that may not be acceptable for larger holes such as tooling and mounting holes. Inner-layer copper must also be cleared back from the non-plated hole, in order to prevent shorts: 230 µm minimum clearance is recommended to ensure good sealing of the laminate.

Single-sided plated holes

Occasionally component designs call for a plated through-hole with a copper pad on one side only. This is a difficult operation to complete successfully, and fabricators may be unable to give any guarantee of plating in the barrel of the hole. This is because the holes become partially tented by photoresist before the plating operation, which inhibits effective movement of the plating solution in the hole, leading to poor plating, as indicated in Figure 5.

Figure 5: Potential problems with single-sided plated through-holes

Potential problems with single-sided plated through-holes

Unless cost is a real issue, you will get better results with single-sided PTH boards by starting with double-sided laminate and using an expanded (0.2 mm greater diameter) drill mask to pattern the component side. This gives perfectly plated holes and a 0.1 mm annular ring on the surface.

Self Assessment Questions

From the description above, produce your own summary of drilling recommendations.

compare your answer with this one

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Inner copper layers

Any fabricator will introduce a number of changes to the original design, in order to make sure that the customer gets what was asked for. Some of these changes are less obvious than others and are discussed in the sections that follow:

Track width and spacing

The chemical and photographic processes used to fabricate a board put constraints on the minimum width of track and on the minimum spacing between tracks. If a track is made smaller than this minimum width, there is some chance that it will open (no connection) when manufactured; if two tracks are closer together than the minimum spacing, there is some chance they will short when manufactured. These parameters are usually specified as ‘x/y rules’ or ‘track/gap rules’, where x is the minimum track width and y is the minimum track spacing. These rules (especially spacing) apply to any metal on the board, including pad to track spacing.

In some parts of the industry, imperial measurements (in thousandths of an inch) are still used to specify minimum track width and spacing. For example, ‘8/10 rules’ indicate 8 thou (0.2 mm) minimum track width and 10 thou (0.25 mm) minimum track spacing, and ‘6 thou track and gap’ indicates 6 thou (150 µm) minimum track width and spacing. However, in the UK, process rules are now more likely to be stated in µm, as shown in Table 4.

Table 4: Inner layer design categories
volume capability
dimension no review DfF review pilot/special
core thickness
100 µm
75 µm
50 µm
core thickness (differential copper)
350 µm
250 µm
<250 µm
plated core thickness
150 µm
125 µm
100 µm
copper thickness
18–70 µm
105–140 µm
etched track/printed gap
½ oz
75/75 µm
50/50 µm
1 oz
100/100 µm
75/100 µm
2 oz
150/150 µm
125/125 µm
min. pad to track
½ oz
90 µm
75 µm
plated core thickness
150 µm
125 µm
100 µm
plated core track/gap
125/125 µm
100/100 µm
75/100 µm
plated core annular ring
150 µm
125 µm
100 µm
min. annular ring
150 µm
100 µm
75 µm
min. PTH to copper
225 µm
175 µm
150 µm

These dimensions are moving inexorably downwards. Once a rarity, modern boards often have some areas with 4/5 (100/125 µm) rules. Note that the smaller of the two dimensions will always be the track width, because this leads to better yields: processes are less likely to cause open-circuits by over-etching than they are to yield short-circuits.

Of course, one reason why dimensions are moving downwards is that auto-routing tends to make overmuch use of minimum design criteria. In the example shown in Figure 6, some tracks have been designed on 75/100 µm rules, which will incur a cost penalty, whereas room is available for a much more conservative layout.

Figure 6: Auto-routing producing a design that is not cost-effective

Auto-routing producing a design that is not cost-effective

Copper balancing on internal layers

The general concept of copper balance is to evenly distribute copper on both sides of the PCB, and also within each side. As we will see when considering outer layers, a balanced copper pattern is important for even plating distribution, but for inner layers the main consideration is to create a balanced lay-up, giving a board that will not warp during subsequent heat processing.

Figure 7 shows ‘before and after’ pictures of an internal PCB layer: before copper balancing the layer has areas with sparse copper tracking that will cause problems for the fabricator; after copper balancing has been added, the previously bare areas have been filled with isolated copper dots.

Figure 7: An internal layer with and without copper balancing

before copper balancing

before copper balancing

the same layer plus copper balancing

the same layer plus copper balancing

There are some general points to bear in mind when designing the copper balancing:

Copper balancing may be carried out by designer or fabricator. If the latter, the board specification has to specify the rules to be applied, and it becomes very important that the designer should indicate clearly on the individual design any areas where adding copper might affect circuit performance.

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Outer copper layers

Track width and spacing

The comments made for inner copper layers apply equally to outer copper layers, except that the dimensions are generally different. This reflects both the additional functions of the outer layers (used for component attachment and test probing) and the fact that outer layers are plated as part of the through-hole fabrication process. Table 4 gives a typical set of process rules.

Table 5: Outer layer design categories
  volume capability  
dimension no review DfF review pilot/special
aspect ratio
for hole size
0.25 mm
6 : 1
8 : 1
10 : 1
<0.4 mm
7 : 1
11 : 1
panel thickness dictated
³0.4 mm
7 : 1
12 : 1
base copper thickness
12–70 µm
105 µm
9 µm; >105 µm
etched track/
printed gap
½ oz
75/100 µm
75/75 µm
<75/75 µm
1 oz
75/100 µm
75/75 µm
<75/75 µm
>1 oz
150/150 µm
125/125 µm
copper in PTH
(min. average)
25 µm
abs. min. 25 µm
to 40 µm
copper in BV
(min. average)
15 µm
to 25 µm
min. a/r for tangency
125 µm
100 µm
75 µm

As with inner layers, the trend in these dimensions continues downwards, and there is a preference for the smaller of the two dimensions to be the track width.

Copper balancing on external layers

Plating thickness varies according to the presence or otherwise of adjacent copper features. In general, it may be said that the more areas you are trying to plate, the thinner the copper will be. Conversely, when one plates isolated tracks, the plating thickness can be substantially greater than one wants. As shown in Figure 8, although the process conditions are identical, the plating thickness on a track becomes progressively thicker as the track moves further away from other tracks. This can be explained in simplistic terms as being due to the isolated pad experiencing less competition for current and the availability of metal in the plating solution.

Figure 8: Heavier plating on isolated copper features

Heavier plating on isolated copper features

But does a thick track matter? Not from the point of view of conductivity, and the extra width will not matter if it is isolated. There are, however, two important effects of which you must be aware. The first of these is on the thickness of the solder mask coat: thick copper will give a locally thin coat, with the potential to break down. There is also the mechanical effect on the board, where unbalance may lead to subsequent warpage.

The magnitude of the difference between isolated pads and tracks close together is demonstrated clearly in Figure 9. Not only is the plating on the isolated pad much thicker, with a substantial degree of edge distortion, but the solder mask coating is very much thinner.

Figure 9: Example of over-plating of copper feature

Example of over-plating of copper feature

A second problem with heavier plating on isolated copper features, and the greater of the two when it comes to high frequency designs, is maintaining control of impedance values. ‘Mushrooming’ affects the track widths and entraps dry-film resist between the tracks, which eventually retards the etching. The effect is similar to that of over-plating tin/tin-lead resist which was illustrated in More about board fabrication, and is especially likely to happen with differential pairs. The resultant ‘raggy’ tracks give ohmic values outside the normal accepted 10% tolerance.

You may have noticed the term ‘well-robbed’ in Figure 9. This relates to the usual practice of attempting to even out copper distribution on the board by adding areas of spare copper, so that the electrolytic plating process can add equal amounts of copper across the board without creating a thicker copper deposit on less-populated areas. These areas of spare copper are isolated from each other and from any active tracks. Because they act by attracting excessive copper plating away from otherwise isolated tracks, these areas are referred to as ‘robber pads’ or ‘copper thieves’. (Figure 10) The patterns used vary, being sometimes arrays of dots and sometimes cross-hatching.

Figure 10: Addition of copper robbing

Difficult to plate evenly due to isolated tracking

Difficult to plate evenly due to isolated tracking

Solution: Robbing added in an attempt to even out copper distribution

Solution: Robbing added in an attempt to even out copper distribution

Self Assessment Questions

Can you describe the following features and explain why they are used:

  1. Copper balancing on internal layers

  2. Copper balancing or robbing on external layers

compare your answer with this one

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Other copper design issues

Bottlenecks

Not all copper features are tracks and pads. Particularly with complex designs that have been extensively reworked, or where additional copper areas are used for screening or ‘thieving’, there may be instances of conductor narrowing, producing narrow strips of copper referred to as ‘bottlenecks’. As these can lead both to open-circuits and short-circuits (where copper slivers can become detached during the fabrication process), it is important to detect bottlenecks.

There are two broad types:

Some examples of bottlenecks are shown in Figure 11:

Figure 11: Four examples of copper bottlenecks (Valor)

Four examples of copper bottlenecks (Valor)

Removal of non functional pads and tracks

One of the ‘cleanup’ procedures that a fabricator will carry out on a layout is the removal of any non-functional pads (NFPs) or tracks. Figure 12 shows an example of a ‘non-terminated vector’, where it is not clear from the design whether this track is a remnant from a previous design iteration, or is an intentional feature.

Figure 12: A non-terminated vector – is this intentional?

A non-terminated vector – is this intentional?

The fabricator will query every unterminated track, so time can be saved if the designer tells the fabricator which NFPs are intentional. Figure 13 is an example of tracks which may or may not be designed to function as shielding tracks.

Figure 13: Non-terminated vectors that may be shielding tracks

Non-terminated vectors that may be shielding tracks

Internal pads

In order to provide the best reliability of construction, it is usual for through-holes and vias not to have associated pads on internal layers except where they are actually electrically connected to tracks on the layers.

There is, however, a case to be made for the designer setting the CAD program to create such pads automatically, and for the board specification requiring the fabricator to remove unused pads as part of the CAM process. This may appear somewhat bizarre, but having internal pads forces the CAD program to allow sufficient clearance between internal copper tracks and through-holes, preventing problems such as that shown in Figure 14.

Figure 14: Violation of plated through-hole to copper spacing

Violation of plated through-hole to copper spacing

Thermal vias

Thermal vias are commonly used to improve heat transfer, and therefore often occur closely spaced. Figure 15 shows an example of poor design, where the net list will show the thermal vias as being connected, whereas the overlap between adjacent thermal vias means that the central vias will be ineffective, because the thermal spoke connection is only 0.0005 inch.

Figure 15: Inadequate thermal pad design

Inadequate thermal pad design

Note that in this figure it is the copper areas that are shown in black

Autorouting problems

We have already seen from Figure 6 that autorouting may result in specifying areas with tracks and gaps that are too tight. Figure 16 is another example of sub-optimal design; of the three areas highlighted:

A represents a particular problem, where rounding during etching will result in narrowed tracks, but will also create problems when scanning with some AOI machines
B shows an unnecessarily tight gap due to auto-routing and no clean-up routine
C shows typical same-net spacing violation.

Figure 16: Sub-optimal design from auto-routing

Sub-optimal design from auto-routing

The ‘ziggurat’ effect noted above is just one example of autorouting creating unnecessary problems for the fabricator. In Figure 17 and Figure 18, we see other examples of poor practice, which will produce faults with photoresist and etching.

Figure 17: Auto-route requiring clean-up by the designer

Auto-route requiring clean-up by the designer

 

Figure 18: Two examples of same-net spacing violations

Two examples of same-net spacing violations
Two examples of same-net spacing violations

One of our reviewers commented “Anyone who still has an autorouter that produces howlers like these should either invest in a decent auto-router or remember that the ‘A’ in CAD stands for ‘aided’, and not be afraid to route the occasional track manually!” But there was a counter-argument from a fabricator who maintained that auto-routing is still a major source of problems:

"Although clean-up routines are widely available, these are rarely used to full effect. Most CAD guys I speak with are always pushed for time and tend to be presented with last-minute component changes from the electronics guys. These are incorporated manually, and the final clean-up/DfM checks are operations that are bypassed to “save time”."

In the original email there were many exclamation marks following that final phrase!

Note that the CAM will not allow the fabricator to rectify complex errors, which must be returned to the layout designer, incurring delay to the project. However, there are some types of problem with which the fabricator would normally deal, and examples of this are shown in Figure 19. The areas marked would normally be filled, to prevent problems either from acid trapping causing over-etching or from slivers in the photoresist potentially becoming detached during photo-imaging processes in fabrication.

Not only do pieces of detached photoresist change the intended pattern, but they can be deposited in unwanted areas. The piece of photoresist will stop the tin etch resist being plated, allowing the etch to eat into the unprotected copper below the resist flakes, and causing ‘opens’.

Figure 19: Potential areas for photoresist defects

Potential areas for photoresist defects

Spacing issues

Finally in this section on copper design issues we have to consider some more clearance requirements. For example, Figure 20 has a test pad enclosed within a copper land, and correctly isolated from it, as the net list will demonstrate. However, it lacks the 0.25 mm clearance necessary to ensure maximum first time pass rates at electrical test.

Figure 20: Leave space for electrical test!

Leave space for electrical test!

Figure 21 shows insufficient clearance between copper tracks and non-plated through-holes of different dimensions. The clearances to copper allowed in this case are 0.05 mm for the small hole and 0.1 mm for the large hole. With drilling inaccuracies of the order of 0.08 mm, the risk of open-circuits is substantial.

Figure 21: Insufficient clearance between NPTH and copper

Insufficient clearance between NPTH and copper

Self Assessment Questions

Identify as many as possible of the kinds of problems related to copper features that the designer can create for the fabricator. How does the CAD system, in particular the way that auto-routing is used, contribute to these problems?

compare your answer with this one

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