In Units 8 and 9 we have already discussed examples of thermal calculations involving semiconductor packages and their constituent parts, and in Unit 12 we will be attempting to give an insight into the types of component model used by thermal modelling packages. So in this Unit, which you should be reading in parallel with Units 11 and 12, we are reminding you of how packages are made, with an emphasis on some of the thermal aspects.
Semiconductor assembly has developed substantially over its 45-year history, moving from simple transistor packages, through to simple integrated circuits to processors and gate arrays that may have literally thousands of connections. As you will know from your own work, the trends are towards greater variety and ever-decreasing size. As a result, from the thermal engineer’s point of view, products that appear similar may in fact have significantly different thermal characteristics, reflecting the differences in internal construction.
For a view on the way in which microprocessor packages have developed, from the earliest 40 lead DIP to BGA styles, see this Intel paper on The evolution of microprocessor packaging (PDF file, 465KB). This paper also has an insight into the challenge of providing sufficient supply current – with current processes requiring 10–20 amps, and expected to increase in the future, the package has to provide very low resistance paths.
In terms of construction, devices can be broadly split into devices with external leads around the periphery and ‘area arrays’, where the connections are brought out underneath the device and not just at the edges.
Looking at each of these in turn; most present-day leaded devices have the general structure shown in Figure 1, the die being attached to a ‘paddle’ or ‘flag’ on a lead-frame, providing a thermal (and usually electrical) path to the die reverse. Connections are then made between the die surface and the lead-frame by wire bonding, and the packages completed by transfer-moulding of an encapsulation material, usually a modified epoxy.
After encapsulation, the lead-frame is plated, cropped and formed, ready for coding and final testing. Whilst the final format varies considerably, both the gull wing of the QFP and the J-lead of the PLCC are made by what is conceptually the same process.
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In the area array, the lead-frame is replaced by a substrate, and the connections from the die made by wire bonds are taken through vias in the substrate to solder ball connections (or equivalent) on the underside. In the most common form of area array, the encapsulation is again provided by transfer moulding.
The connections to the area array will be made with solder, some of which is brought to the joint in balls or columns previously reflowed to the device (Figure 3).
Where the underside of the device merely has solderable areas, as in the LCCC or LGA, the whole joint is created at the assembly stage using solder paste (or, more occasionally, conductive resin).
It is quite clear that the die in the BGA is in much closer proximity to the final connections than is the case with a leaded device, and it should be little surprise to find that, with this style of area array, the bulk of the heat is transferred by conduction through the base.
Lee and Luo Design characteristics of high-performance and reduced cost CSPs (PDF file, 1.26MB) show, for a µBGA package based on a polyimide flexible substrate, how much of the heat goes through the balls, and how little through the top surface of the package. This is demonstrated by the relative insensitivity to changes in the local air velocity of the overall thermal resistance from junction to ambient.
However, trapping the heat under the component may not necessarily offer an easy route for thermal management, so other styles of area array have been developed in which the main thermal path is to the top surface of the package (Figure 4). As this surface is more accessible, and adding a simple heat sink is relatively easy, this is a package frequently employed for high-dissipation chips.
With both styles of package there are alternative ways of making connections to the die, by wire bonding and by solder bumps. In the latter case, the ‘flip-chip’ technology shown in Figure 5 (and first envisaged by IBM as early as 1964) is used to make all the bonds in one pass, potentially cost-reducing the process and also reducing the thermal resistance between die and mounting plane. The ‘underfill’ resin, applied mostly to improve the mechanical performance and life of the joints, also provides a thermal path away from the die.
Source: Speedline Technologies
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But these two generic styles are not the only possibilities. In recent years, the pressure to produce substantially smaller packages has resulted in moves in two directions:
For the latter, there are many different constructions, one of which is shown in Figure 6 – John Lau’s book2 Chip Scale Package describes four generic types and over 30 package variants – and this was relatively early in CSP development! Although there has since been some rationalisation, considerable variation still exists.
Source: Speedline Technologies
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Before the advent of the plastic-encapsulated microcircuit, all semiconductors were assembled within hermetic packages, where the IC and its bonds were in a volume defined and protected by the package, and filled (hopefully) with dry air (Figure 7). Confusingly, some of the terminology used then is still used for microcircuits where the cavity has been replaced by a plastic moulding, and the construction is solid.
Traditionally, the die was attached to the inside bottom of the package. Referred to as “cavity up”, this has been a standard IC assembly method for over 30 years, although it does not provide the best thermal characteristics. For this reason, many large Pin Grid Arrays, copper-based BGA packages and ceramic quad flat packs are assembled “cavity down”, with the die attached to the inside top of the package in order to improve the heat transfer to the ambient air (as in Figure 4).
Typically users have to take what they are given, but quad flat pack leads can be formed towards either side, provided that the usual care is taken to avoid package damage during lead forming.
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Whilst it would be unrealistic for designers to know in detail how the packages they specify are made, it is important that they should understand something of its construction in order to take an informed view of the potential for unreliability of a package. However, from a thermal perspective, any kind of internal construction can be modelled, and the manufacturer can provide sufficient information for an accurate simulation without having to reveal to the world how this has been achieved. How this is done we will be seeing later in the Unit.
In the light of what you know about package design and materials, try and identify the elements that affect the internal thermal performance of a semiconductor component (as distinct to the elements that are affected by the conductivity of the test board, and its configuration, and the.
When you have done this, look at our comments.
Particularly with devices that are thermally challenged, substantial variations will be made to package design in order to enhance performance. A typical example is shown in the cross-section of Figure 8. Here a separate thermal plane of copper has been integrated in the package, separated from the die by the die paddle, and its presence totally unsuspected until the device was sectioned! Unfortunately, in this photograph the (very thin) bond line between spreader and paddle is obscured by grinding marks, so identification is not possible, but such bonds may be metallic (solder or fusion weld) or made by resin. The choice of method will affect the thermal performance; as we will see later, information about this can be found by examining the response to thermal transients.
The section was taken near the corner of a QFP, so a number of wire bonds were intersected
A point to note with all thermal design is that the performance of real parts is highly dependent on the manufacturer. Whilst there are generic formats, the performance of nominally identical packages will vary according to the choices made, and the values you insert in your thermal model should be those from the manufacturer of your part.
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The measured thermal resistance will be highly dependent on the configuration and size of the board onto which the component is mounted, and other practical effects cause variation. Two examples are quoted in the Philips Semiconductors booklet Thermal design considerations:
When we measure real parts we must also expect some variability between components from different manufacturers, as a result of differences in design and materials.
We have already made the comment that there are considerable variations between manufacturers, depending on the choices they have made as to the materials used and the detailed design of the component. Taking two aspects that relate to lead-frames:
There are significant differences in conductivity between copper-rich materials and Alloy 42. In early DIPs, Alloy 42 was chosen for lead-frames as it gave a favourable combination of strength and ease of forming. However, as integrated circuit packages have continued to shrink and demand more current, there has been a switch to copper alloys for lead-frames as these give higher conductivity, both thermally and electrically. Copper alloys are essential for “Thin Shrink” packages such as the TSSOP, where the lead-frame thickness is constrained by the overall package size.
From the design perspective, even though there is a specification for lead-frame thickness within the JEDEC outline, there is always scope for one manufacturer to choose to operate near the top end of the allowable range, and another to decide to manufacture at the bottom limit.
Assuming that you are dealing with reputable manufacturers, who have made informed design decisions, you will be able to quantify the variations and act appropriately. However, you should be aware that a number of counterfeit parts are in circulation. These appear similar to the full-price original, but fall short in many respects. And this is not as simple as buying a CD “off the back of a lorry”. There you may find the music of poor recording quality, but the CD itself is likely to meet normally-accepted standards, and at least not damage the equipment playing it. In the case of the counterfeit component, not only is the electrical performance suspect, but shortcuts will almost certainly have been taken during the construction. These may have considerable impact on the thermal performance, as you will see at this web site. Hopefully you won’t find any counterfeit parts in your plant!
Finally, be aware that the thermal parameters quoted for a package are for the component as originally supplied. As this paper points out, moisture absorbed in the package that is displaced during heating can result in delamination, and such delamination has a dramatic impact on the ability of the package to transfer heat, because it creates additional high-resistance interfaces. With moisture sensitivity of components becoming more critical as a result of the higher temperatures needed by lead-free soldering, manufacturers must be more aware of potential for modifying performance unintentionally, and the need to adopt appropriate safeguards.
In the Microchip design note ADN005 Bonnie Baker makes the comment that “Smaller Packages = Bigger Thermal Challenges” . . .
In the sense that smaller packages have higher dissipations per unit of area, Baker is correct, but many circuits have considerable challenges within quite ordinary packages, merely as a result of the chips having higher dissipation.
B. M. Guenin, A. Chowdhury, R. Groover, and E. J. Derian, Analysis of Thermally-Enhanced SOIC Packages, IEEE Trans. Comp., Packaging, Manuf. Technology (PDF file, 634KB)
Whilst now quite old, this paper is still interesting in looking at the different ways in which something even as simple as an SOIC can be enhanced by modifying the lead-frame, although improving the moulding compound has little effect. The team used finite element analysis, but a package in which it was possible to represent the package internals with a high degree of accuracy. The number of elements was kept relatively low (typically 1,200 elements) by devices such as using considerations of symmetry to compute the performance of just one quadrant of the package.
The most significant improvements to the thermal performance of the package were with designs in which the die was connected to a heat slug integral to the lead-frame or where the leads directly contacted the die. Note that this ‘chip-on-lead’ design requires the reverse of the chip to provide electrical isolation between the leads, as well as isolation between the leads and the circuit elements on the die.
We have already seen (Figure 4) the style of face-down BGA with enhanced thermal properties that was characterised by Guenin and his team from Amkor Electronics. Their ‘superBGA’ package is a die-down design, a key feature being the heavy-gauge copper-alloy backplane to which both die and laminate are directly attached. The die is positioned in a cut-out within the laminate, so that the package can be made in much lower profile than a conventional BGA.
After wire bonding, a liquid encapsulant is applied to the die area to protect the die and bond wires, being kept within the required area by a resin dam previously applied to the outer surface of the laminate. Vias connect the internal power and ground planes to the solder balls on the underside of the package, but the signal traces are on the underside of the laminate, routed to the balls without vias, in order to reduce the track length.
The backplane is key to the thermal performance of the SBGA, as it couples heat between the other package components, spreading power for the die over its entire area, and lending itself to further enhancement by applying an external heat sink. Having power and ground planes not only provides low-inductance power distribution, but also reduces the signal line inductance.
Guenin et al, Analysis of a thermally-enhanced ball grid array package
Guenin et al, A study of the thermal performance of BGA packages
The importance of the substrate in determining the thermal properties of a package has been reinforced by Ramakrishna and Kent7. Modelling a PBGA under natural convection conditions using CFD tools, they found that the maximum junction temperature was little affected by the thermal conductivity of die attach material and moulding compound, but that increasing the thermal conductivity of the substrate (for example by increasing the number of vias) could reduce the maximum junction temperature by as much as 10°C. They also reported that the temperature distribution on the surface of the component was not uniform, and the spreading resistance between the die and mould surface was a significant proportion of the junction-to-case resistance.
When modelling a package, we have to take great care that we know what we are using; the effect of copper thickness alone is shown in Figure 9. And it is not just the conductors where we may have less than perfect information; Rosten et al.8 found that the thermal resistance of the moulding compound was substantially higher than the value given by the manufacturer of the material, which the team believed to have been calculated synthetically rather than obtained by direct measurement.
Source: B. Guenin, Semitherm XIV, 1998
Achieving increased power density is particularly important for portable applications. Whilst generally the focus has been on the silicon-to-footprint ratio, the die area divided by the overall space taken, this can also be an indication of power density for devices such as MOSFETs. International Rectifier9 express one performance measure for their (products) as a figure of merit (FOM) calculated as the product of the footprint area and the device RDS(on).
SOT-23 and TSOP-6 packages frequently used for power MOSFETs have silicon-to-footprint values of around 20%, as against alternative packaging methods. Merely removing the leads, so that the joints are underneath the chip, doubles the silicon-to-footprint ratio, whether this is done by an SON type package or a BGA. The ultimate of course is to passivate and bump the chip to provide direct contact between silicon and board. At the same time as improving thermal performance, the height of the package is also substantially reduced. But that isn’t to say that the FlipFET is not without its problems. For example, flip-chips generally need underfilling in order to provide appropriate reliability, and the format depends on heat being taken through the solder balls, as it isn’t possible to add a heat sink to something so small!
Design Characteristics of High Performance and Reduced Cost Chip Scale Package – µBGA by Lee and Luo, which we referred to in an earlier section, has interesting information on the chip-scale approach to achieving a high FOM.
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The first two of these lists are in the order in which the material is referenced in the Unit text. However, note that the links to the SAQ answer is not included!
Within our Topics area there is an outline paper on Semiconductor packages, and significant detail on each of the semiconductor back-end processes:
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