Design for Thermal Issues

Unit 12: Modelling components

Device modelling is an important topic that is fundamental to making accurate thermal predictions, which is why it has been a theme throughout recent Units:

In this Unit we will be examining some of types of model that have been developed, built at different levels of complexity and accuracy for different applications. We will be concentrating almost exclusively on semiconductors, as these are the most common sources of heat on a board, and they present complex situations, with many thermal pathways and variations in design and performance. However, the same concepts apply to all other heat-generating components: as an example, we have included a reference to a paper showing the modelling ideas applied to the heat generated within a transformer.

Unit contents


Modelling is one of the major issues in thermal design, and has been a subject of discussion for many years. The issue is regrettably complex, as is its treatment in the literature, with many academic and technical papers being produced, so we suggest that you take time to read the Unit text carefully, and refer to some of the papers we have referenced.

In Unit 11 we recommended that you read a paper by Valenta1 which showed an example of a simulation applied to a ball grid array, and the close correspondence between measurement and calculation. From this you might well have concluded that simulation programs should always build up an exact physical model of each device, assign the appropriate material parameters, and compute the heat flow in detail.

Unfortunately, whilst this looks fine in theory, in practice working at this level of detail results in models that are far too complex, where the solution will probably not converge at all, and certainly not within an acceptable time. And, of course, such a model needs a full computer simulation and is not amenable to hand calculation or using a spreadsheet.

1 Thermal Modelling of Ball Grid Arrays, Pavel Valenta, 5th International FLOTHERM User Conference, Paris, September 1996


There is also some danger that the model may not represent the real device – the modelling technique, the accuracy of the detail, and variations in materials may all contribute to this. For all these reasons, most packages will use a simplified representation of the device, either provided by the manufacturer or calculated using one of the specialised tools available.


The science of thermal modelling has developed over the past 40 years primarily as a response to the question “How hot will this junction get with a specified dissipation, and in a given situation?” As Noebauer and Pape put it in the introduction to their paper Thermal characterisation of active components, “If correct and simple thermal models of critical components are available, it becomes possible to calculate their junction temperatures with sufficient accuracy to serve as input for reliability analysis.” And, whilst simple models should not be expected to yield high accuracy, they are useful both for early estimation and for final sanity checking.

The basis of modelling heat flow

Single-parameter approaches

The concept of thermal resistance gives us a general solution to the question “How hot will this junction get?”

$T_J  = \frac{P}{{R_{th} }} + T_A $

where TJ is the junction temperature, the power P is measured in watts, Rth (or Θ) is the thermal resistance of the path in K/W, and TA is the ambient temperature. Although we would need to consider all the potential routes through which heat passes in order to obtain an accurate overall solution, keeping the approach simple means using as few parameters as possible to describe the package. In this section, we are examining two single-parameter approaches that have been used to estimate chip temperatures and, rather more successfully, to compare different packages.


If there is reason to expect that the outside of the component will be at a known temperature, for example where the part is associated with a heat sink or board with a heavy copper content, then we can employ a single-parameter thermal model that describes the heat flow to the case, using the equation:

$T_J  = \left( {\Theta {JC}  \times P} \right) + T_C $

ΘJC, the junction-to-case thermal resistance, is defined at the exposed surface, and can be used to estimate the thermal performance of a package, where it will give accurate results if there is negligible heat flow from the package to the board and if the case is kept at a uniform temperature, for example by using a heat sink or thermal spreader. Where significant heat flows through the leads, or if the case is not at a uniform temperature, this model is not appropriate, although it will usually give a conservative result.

But how do we measure this parameter for a real package, rather than rely on analysis to create a theoretical value?


Work originally carried out for the US military, and followed by studies by SEMI (a semiconductor industry association), sought to give representative figures for thermal parameters based on measurement. Read about the standards and the ways in which testing is carried out in the first two sections of our paper on Measuring thermal parameters.



The second common single-parameter thermal model uses a ‘junction-to-ambient’ thermal resistance, ΘJA, that measures the conduction of heat from the junction, the hottest place on the die, to the environment near the package. Heat travels by convection and radiation from the exposed surface and by conduction into and through the test board, followed by convection and radiation from the exposed board surfaces. ΘJA therefore reflects how well heat flows through all the available paths from the junction to the surroundings. The ΘJMA parameters are the equivalent thermal resistances, but with forced convection (MA = ‘moving air’).

The resultant junction temperature is related to power, ambient temperature, and junction-to-ambient thermal resistance by the equation:

$T_J  = \left( {\Theta _{JA}  \times P} \right) + T_A $

However, because ΘJA is the result of many thermal paths, this parameter can only be relied upon to give a reasonable estimate if the application conditions, in terms of airflow and board mounting, are very similar to those under which the component was characterised. As real situations rarely correspond with the test methods2, and the value of ΘJA is influenced by the board type and the air velocity, its use for predicting junction temperature is fraught with difficulty, and has rightly been criticised.

2 The tests are described in JESD51-2: Integrated circuit thermal test method environmental conditions – natural convection (still air), and JESD51-6: Integrated circuit thermal test method environmental conditions – forced convection (moving air).


Another note on nomenclature

Although the word is not in everyday use, for unknown reasons we often use the term ‘ambient’ (from the Latin “to go on both sides”) to describe the surroundings of the item being discussed. Thus “ambient temperature” means the temperature of the surroundings, and ‘ambient’ is also used as a noun, equivalent to ‘surroundings’.

But this second use is generally in the sense of the temperature of the surroundings (“in this ambient the maximum dissipation is . . .”), whereas the similar word ‘environment’ can imply that other aspects such as humidity are important (“the engine compartment of a car is a harsh environment for electronics”).

Watch your words . . . in Alice Through The Looking Glass, Humpty Dumpty declared that “When I use a word, it means what I want it to mean, nothing more, nothing less.” Alice was right to dispute that!


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Characterising a package

A typical package will be characterised by its manufacturer in more than one way, and several different parameters will be quoted, as shown in Table 1, which is an extract from Freescale Application Note AN2388/D:

Table 1: Thermal resistance data for HSOP packages
thermal path
board type
junction to ambient natural single-layer (1s)
junction to ambient natural 4-layer (2s2p)
junction to ambient 200ft/min forced single-layer (1s)
junction to ambient 200ft/min forced 4-layer (2s2p)
junction to board
junction to case
junction to package top natural

Note that, in line with JESD513, some parameters have been measured on two different boards, one with a single layer, and one with heavy copper and two internal planes. Changing the board makes such a big difference that the obvious conclusion must be that, for this particular package, most of the heat is escaping by conduction through the board. This is confirmed by the observation that, whilst the values for ΘJMA are lower than those for ΘJA, the change is smaller than the reduction that comes from improving conduction.

3 The two boards are described in JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.


The manufacturer’s expectation is that most applications will exhibit thermal performance that is intermediate between the test conditions under the appropriate convection regime. Values at the top of the range will be reasonable estimates for package performance either with a low conductivity board or where the part is on a conducting board but tightly populated with similar components; values at the bottom end of the range will give a better prediction when there are no nearby components dissipating significant amounts of heat.

Key information

The values of thermal resistance from the junction either to ambient or to case are still useful for their original intention of allowing packages to be compared in terms of their operation in a standardised environment. But the junction temperatures, the flow of heat through the package, and the thermal resistances that result, are all strongly dependent on how cooling is being carried out. Standardised values of ΘJA and ΘJC are therefore of limited value to end-users for characterising the thermal behaviour of the component in an application, unless their environment happens to be the same as that used for the test.

This criticism is particularly applicable to ΘJA – for applications where the semiconductor is directly coupled to a heat sink, so that the bulk of the heat transfer is by conduction rather than convection, and thus subject to fewer variables, ΘJC typically gives sufficiently accurate estimates of junction temperature.


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Improving the model

Moving towards BCI models

From the component supplier perspective, it is clearly not possible to supply thermal data for all combinations of package and environment, which is why the JESD standards have evolved. The only feasible way of overcoming this challenge is to make a clear distinction between the package and the environment, ideally providing information on the device that will allow an accurate model to be created regardless of what is happening outside the package boundary. By making the model less dependent on the external conditions, the calculation of junction temperature will be accurate whether the component is in still air, forced convection, or fitted with a heat sink. This is what thermal engineers refer to as a model that is ‘Boundary Condition Independent’ (a ‘BCI model’). As we shall discover in the following sections, creating a simple, accurate and validated BCI model continues to be the aim of modellers. This approach assists greatly in dividing the thermal management task between component manufacturer and user, the manufacturer being responsible for giving the user a model of the component that can be incorporated into an analysis of the wider system.

The approach that Freescale chose (Table 1) was to split the ΘJA component into two parts, the thermal resistance of the package from junction to board, and the contribution of the thermal resistance from board to ambient ΘBA. ΘJB, the junction-to-board thermal resistance, measures the horizontal spread of heat between junction and board, the board temperature being taken near the board surface on one of the central package leads, as described in JESD51-8. This parameter is very much lower than ΘJA because it represents only part of the total thermal resistance from junction to surroundings. The relationship between ΘJC and ΘJB will depend strongly on the package type, but ΘJB is usually substantially higher, because the heat path is mostly through the leads, whereas in many power packages the die is bonded directly to the case.

Whilst ΘBA is outside the scope of the component supplier to influence, ΘJB can validly be used to compare different packages, in the same way as can values of ΘJC. This division of responsibilities is helpful both to the component manufacturer, who may not wish to disclose information about the internal instruction of the package, and to the system designer, whose simulation might struggle to handle the amount of data involved with more detailed component models.

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Theta and Psi

So far, we have explained all the elements in Table 1 except the final row, and ignored the implicit question – Where does the Ψ parameter come from? There are actually no fewer than five common package performance metrics that it is important to understand:

For a single-chip package, any thermal metric is calculated by measuring the difference between the junction temperature and a reference temperature in a specified environment and dividing it by the total power. But the meaning, values and limitations of use of the resulting metrics are highly dependent on the way that the heat actually flows.

Taking the general case, as in JESD51-1, a ΘJX (thermal resistance) metric measures the ease of heat flow between the junction and a defined environment whose reference temperature is TX:

$\Theta _{JX}  = \frac{{T_J  - T_X }}{P}$

For measuring ΘJB and ΘJC, the value of P, whilst being the total power applied, is also a close estimate of the power that passes through the thermal path to the defined environment, as the tests are designed to force as much as possible of the thermal energy along a specific route.

But we can also define other metrics, given as optional procedures in JESD51-2 (Section 4) and JESD51-6 (Section 6.2), that reflect the natural division of power, rather than the artificial conditions of the tests. Again taking the general case, the ΨX (thermal characterisation parameter) metric, is a correlation between TJ and another temperature TX, where only part of the heat flows to the region represented by TX:

$\Psi _{JX}  = \frac{{T_J  - T_X }}{P}$

The Ψ metrics correlate the chip temperature with the temperature of the package top or the board, and are used to estimate the chip temperature in conjunction with models of how the heat then flows from package top or board to the surroundings. Note that, although not all the power applied results in a rise in temperature of the region that is being measured, it is the value for the total power that is used in the calculation. The total power figure is used because it is the only figure that is known with certainty – we can only estimate how much heat actually flows in any specific route. For this reason, ΨJX is not a thermal resistance as such, although it is quoted in the same units.

ΨJT is the junction-to-top thermal parameter that correlates junction temperature with the temperature of the outside of the package, and ‘shadows’ ΘJC in a real world situation. It is measured using the same methodology as for ΘJA, but the temperatures measured are those of the junction and at the top of the package. The value of ΨJT depends on the airflow – in packages provided with a heat sink, where the primary heat flow is almost one-dimensional and the heat flux confined to the top of the package, TC and TT are taken at the same point and ΨJT approaches ΘJC. However, in moulded packages, the one-dimensional condition is difficult to meet, because at best only a fraction of the heat flux, perhaps 50%, is transmitted through the top, even in the standardised set-up. Of course, in the end-user application, the split between heat flow paths may be similar. Clearly in such a case the values of ΨJT and ΘJC will tend to diverge.

ΨJB is a thermal parameter that approximates to ΘJB in a real-world situation, providing a correlation between junction temperature and the temperature of the board, and is measured in the same way as ΨJT, except that the reference temperature is that of the board. Frequently, the junction-to-board thermal resistance will be larger than junction-to-board thermal characterisation parameter. However, since the copper density will affect the results, and ΨJB is measured on a high effective thermal conductivity board, data from this test has to be treated with caution.

There are correlations between many of these metrics. For example, Figure 1 shows the relationship between ΨJB and ΘJA for a range of large BGA packages. And the Ψ values can be used to estimate the junction temperature from a measurement of either the top of the package or the board in actual applications. The problem with Ψ lies in making direct measurements, because these depend on knowing how much of the power leaves from the top of the package, and how much through the bottom.

Figure 1: Correlation between ΘJA and ΨJB (PBGA packages)

Correlation between ΘJA and ΨJB (PBGA packages)

Source: Guenin What are all these different thermal numbers?


“It is . . . essential to note that these standard-based measurements give characterisation results that allow packages and conditions to be compared. Like miles per gallon figures quoted on new cars, the numbers should be used with caution. As specific user environments will not be identical to the conditions used in the characterisation, the numbers quoted may not precisely predict the performance of the package in an application-specific environment.”

Xilinx user guide, Device packaging and thermal characteristics


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Getting an overall picture

So far we have explored two Θ parameters that we can use to compare different packages under the same conditions, and two Ψ parameters that can be used to correlate the junction temperature of a die with the measured temperature on the board. Except in the simplest cases, in order to build a model of the overall situation, we need to combine more than one of these parameters, reflecting the fact that heat flows down several pathways. After all, the alternative of using the third Θ parameter, ΘJA, is not favoured, as the accuracy of predictions depends greatly on the match between the test conditions and the application environment.

But how do we combine them? For example, can we treat the thermal paths as purely additive, as in Figure 2? Here we show two paths to the surroundings, through convection from the case and by conduction through the board.

Figure 2: Is this a valid two-parameter model?

Is this a valid two-parameter model?


It is very tempting to think in terms of the “thermal resistors” on the right-hand side of Figure 2 as being equivalent to some of the parameters that we have described. In other words, Θ12 and Θ34 in parallel would be ΘJA, Θ1 and Θ3 in parallel would be ΘJC, and Θ3 would be ΘJB. Unfortunately, whilst it is correct to describe these heat paths as being in parallel, and it is also valid to assign a thermal resistance to each, we will get totally misleading answers if we perform the calculations using the Θ values of thermal resistance. The reasons for this lie in the way that the measurements are made, in the assumptions that are inbuilt, and in our treating thermal resistance and electrical resistance as being exact analogues.


Think ‘Thermal’, not ‘Electrical’

“Thermal and electrical systems have analogies that many engineers draw upon, but there’s an important difference that might make you want to think about thermal a little differently.

“The ratio of high versus low conductivity items in the thermal world is typically on the order of hundreds-to-one, while in the electrical world it’s trillions-to-one or more. Because of this, an engineer’s thermal “gut feel” may not be quite right when it’s based mainly on electrical engineering experiences.

“Heat doesn’t tend to flow down metal traces from points A to B with little loss like electrical current. Rather, the heat flows much more easily into surrounding materials or the air. All this ‘leakage’ of heat is generally nothing to complain about since we’re usually trying to increase it even more, but it does add a good bit of complexity to the task of predicting how much heat is flowing where.”

Jim Benson, Intersil Technical Brief TB379.3


Figure 3 shows the Figure 2 device split into its components, with separated junction-to-case and junction-to-board thermal paths. It is clear that a value of ΘJC measured between junction and the outside of the case under artificial conditions of heat flow, is likely to be too low; the real thermal paths are longer and more complex, and not all the heat passes through the top surface. By their definition and measurement method, thermal parameters allow for this division of heat flow between different paths, so using ΨJT will give us a more accurate assessment, but only if the application environment is similar to the conditions of measurement.

Figure 3: Models of junction-to-case (left) and junction-to-board (right) thermal resistance

Model of junction-to-board thermal resistanceModel of junction-to-case thermal resistance


In a natural convection situation, much of the heat will flow through the leads of the gull-wing style of device indicated in Figure 3, so we will probably get better estimates by using the ΘJB parameter, as indicated in the right-hand diagram. However, this ignores any effect resulting from the main pathway being shared, as heat flowing through the leads goes both to the board and to the package exterior. As with the junction-to-case parameter, ΨJB should give us a more accurate assessment, but only if the application environment is similar to the conditions of measurement.

If we fit the device with a heat sink, as shown in Figure 4, thus increasing the percentage of thermal energy flowing from the top surface, we will get closer to the conditions that are represented by the ΘJC parameter. [ΘHSA represents the thermal resistance from the package interface to the heat sink through to the suroundings] Whilst there are other thermal paths, these are in parallel with ΘJC, confirming that using this parameter to estimate junction temperature will produce a high value. In other words, the prediction will be conservative (safe) from the reliability point of view.

Figure 4: Model of junction-to-case thermal resistance, with heatsink fitted

Model of junction-to-case thermal resistance

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Lumped elements

Our model in Unit 9, Figure 4 took a simplified view – not quite one-dimensional, as we allowed for some thermal spreading, but it was a simplified calculation nonetheless. But it indicates an approach that can be extended – for example, with a Ball Grid Array, we can think of the ways in which flow of heat might be constricted by the ball and spread through the heat sink. As shown in Figure 5 for a DIP, heat flow can be along the leads, through the base of the device, and to the top surface, each one modelled by a different thermal resistance, and the overall junction-surface thermal resistance is formed by all of these paths in parallel.

Figure 5: Expanded cross-section of DIL package with heat sink, showing resistor analogue

Expanded cross-section of DIL package with heat sink, showing resistor analogue

We have already seen that gross simplifications, where all the thermal paths are treated as a single resistance, have limitations on their accuracy. And the criticism can equally be levelled at the three-resistor diagram in Figure 5 – when we look in detail at a package, we find many different routes. From here it is only a short step to thinking of heat flow as capable of being modelled by a whole network of thermal resistances.

However, we have to decide how detailed to make our model, and to what degree the model should mirror the physical heat transfer. For example, whether a number of leads effectively in parallel should be modelled as a single thermal resistance, even though there may be some variation between the heat flow in each lead, depending on the relative position of the junction.

Most packages are layered structures, combining metals with high thermal conductivity and dielectrics with lower conductivity (very much lower in the case of plastic packages, compared with ceramic styles). Also, mirroring the die dimensions, the lateral dimensions of most plastic packages are substantially greater than their thickness. In consequence, heat flow within the packages is mostly in-plane flow in metals and through-plane flow in dielectrics, with the exception of the heat flow in solder balls (Figure 6).

Figure 6: Heat flow patterns in plastic packages

Heat flow patterns in plastic packages

Source: B. Guenin, Semitherm XIV, 1998

Guenin’s team from Amkor Electronics4 developed a lumped-parameter model for a plastic BGA which made assumptions about the heat flow, but allowed for known effects such as thermal spreading in both the package laminate and the external board and calculated appropriate resistances for conduction and heat transfer coefficients for convection and radiation. As with our simplification in Figure 6, the researchers created a model from which junction temperature could be calculated that bore some correspondence to the real world, but was substantially less complex, the detailed information on materials, dimensions and construction having been brought together and summarised.

4 The original papers by Guenin et al are A study of the thermal performance of BGA packages and Analysis of a thermally-enhanced ball grid array package.


Figure 7 shows their thermal circuit diagram for the SBGA package, interpreting the major paths by which heat flows from the die junction to the surroundings. Some of the heat will flow directly through the over-moulding compound, but the bulk of the heat flows through the die and into the laminate. Here heat flows both directly through the laminate and is spread laterally; some heat will flow into the air through the top of the package, and the rest will dissipate through the package into the board. Note, however, that only the most significant heat flow paths are considered; Guenin and his colleagues defined an insignificant path as one whose omission would change the calculated value of ΘJA by 2% or less. Two examples of such flow paths are from the die to the laminate through the bond wires and through the encapsulant.

Figure 7: Thermal resistance network for a PBGA package

Thermal resistance network for a PBGA package


From the practical point of view, it is noteworthy that less than a third of the thermal resistance junction to ambient is contributed by the package itself, due to the low values of thermal resistance from die to backplane and die to board, and that the latter could be enhanced by applying a thermal filler underneath the package. Removing heat from the top of the package and the underside of the board to which it is mounted becomes the biggest challenge.

The greater the simplification, the easier a model is to use, but the further it departs from the physical reality. Common sense suggests that the model should be based on the internal component structure, should not be influenced by external conditions such as mounting or airflow, and should reflect the heat pathways in the component; however, the really important factor, especially for hand calculation, is that the model should be as simple as possible, consistent with reasonable accuracy and ease of incorporation into a model of the whole system.

To help in later integration, the resistance network used to model a component will normally have elements positioned between the points where heat is generated and where it is dissipated outside the component. This forms a simplified map of a complex reality, not only for the single-parameter Θ situation, but also for most other models, including the DELPHI models.

Mälhammar draws a useful distinction between a physical model and a conceptual model: in the physical model, there is a one-to-one correspondence between heat paths in the real device and resistors in the model; in the conceptual or ‘logical’ model, an array of resistors is devised that has the same thermal performance as the real device, but there is no unique correspondence between heat path and resistor. This is shown schematically in Figure 8.

Figure 8: Levels of abstraction in thermal modelling

Levels of abstraction in thermal modelling


It is this conceptual model that we will find to be the basis of recent work, especially by the DELPHI project and its successors. Given greater computing power and more information, the trend has also been towards models that are more complex, and where a better correlation is established between the model and the performance of the real component. But, beware! greater complexity does not necessarily lead to increased accuracy of prediction.

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Detailed and compact models

The aim of compact models is to capture the thermal behaviour of the package accurately, even though using a reduced set of parameters that need not have a one-to-one correspondence with the physical structure of the package. By using a CFD program to handle the coupling with the surroundings, the resistor network within the package becomes independent of the environmental interaction, allowing the device model to be boundary condition independent.

But what is the best compact model? and how do we achieve it? Referring to Figure 9, we have already seen how physical measurement and analytical approaches can give estimates of model parameters, and indicated something of their limitations. Finite-element simulation methods are an obvious way to approach complex situations, and considerable experience has been built up in this area over the past 15 years.

Figure 9: Some routes towards verified models

Some routes towards verified models



DELPHI was a seminal 1990s project which has given its name to a specific type of compact model. Read our paper on the project, and look at its history and methodology and the tests used.


Detailed model solutions predict the local temperature distribution within a package and provide a complete 3-D mapping of temperatures throughout the package and the board to which it is attached. They are also of real value to package manufacturers, who can easily make parametric changes in the model in order to accommodate modifications to design and materials without revealing proprietary information about the internal construction of packages.

Unfortunately, a detailed mapping is often specific to the software tool employed by the modeller, and is computationally demanding because of its large size, typically thousands of nodes. For these reasons, a detailed model cannot generally be used as a means of transmitting thermal package performance between supplier and customer, so some simplification is necessary.

However, based on the excellent agreement they found between simulation and measured results, the DELPHI project workers proposed that detailed models should be the starting point for creating compact models, which would then be validated and optimised to give the best possible predictions for a wide range of application conditions.


For an example of the work carried out during the DELPHI project, read the report by Rosten and his colleagues, Development, validation and application of a thermal model of a PQFP.

Make notes on how the parts was tested and modelled, concentrating on issues that might affect the accuracy of the model and its computational requirement.

Compare these with our notes.



“A detailed model is a model that attempts to represent or reconstruct the physical geometry of a package to the extent feasible. Thus the detailed model will physically always look similar to the actual package geometry. A properly constructed detailed model is, almost by definition, Boundary Condition Independent (BCI); i.e. the model will predict the temperature of the various elements within the package (including junction, case, and leads) accurately regardless of the computational environment in which it is placed.

“A compact model on the other hand is a behavioral, model, that aims to accurately predict the temperature of the package only at a few critical points - junction, case, and possibly leads. It cannot predict the temperature at any other part of the package. Most importantly, a compact model is not constructed by trying to mimic the geometry and material properties of the actual component. It is rather an abstraction of the response of a component to various boundary conditions.”

Shidore and Sahrapour DELPHI Compact Models Revolutionize Thermal Design



There are differences between authors in the way in which the terms ‘compact’ and ‘detailed’ are used, but ‘detailed’ is most commonly used for models built using finite-element tools, with high numbers of cells and a close correspondence with the physical part, to distinguish them from ‘compact’ models, which are usually conceptual/logical and with relatively few parameters.

When you come to use FLOPACK and other Flomerics products, you will find subtle differences that are not universally employed. As defined by Flomerics, whilst a detailed model is one that presents package details such as solder balls, thermal vias and metal layers explicitly, individual elements such as leads or a solder ball array might still be represented as a single block with lumped thermal properties.

Analytical conduction models, such as those used by Guenin in the articles referenced above, start detailed, but end up as compact. They can adequately predict package thermal performance in simple configurations, and are therefore most useful when package design follows a fixed format. However, finite element approaches are more practical when there are frequent variations in design, and a CFD approach will be most efficient when the bulk of heat transfer is by convection.


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Two-resistor and DELPHI models

The two-resistor compact model (Figure 10) is what we were striving to identify in our earlier discussion (see Figure 12), but note that the values of the thermal resistances generated from a detailed model will not be the same as the nominal Θ and Ψ parameters for the package. The model is easy to work with, even at a spreadsheet/hand calculation level, because it confines itself to the two main thermal paths from a package. However, it has lower accuracy than more sophisticated models, and there is no means of estimating error.

Figure 10: Two-resistor compact model produced by FLOPACK for a 256-lead 28×28mm PQFP

Two-resistor compact model produced by FLOPACK for a 256-lead 28×28mm PQFP


By comparison, the DELPHI compact thermal model represents the package as a network of thermal resistors that accurately predicts the junction temperature independently of the final boundary conditions. The network typically consists of 8–10 resistors that link the junction node (representing the die) to all major surfaces from which heat is extracted. Thermal links are also allowed between the surface nodes (shunt resistors). Schematically, a DELPHI compact model for a leaded package looks similar to Figure 11, and the information is presented in tabular form, as in Figure 12. Although more complex than the two-resistor model, there is a significant reduction compared with the number of nodes in a detailed model, yet the accuracy is typically 95%.

Figure 11: Possible node topology for a PLCC package

Typical DELPHI boundary condition set

Note that the package surfaces have each been divided into several nodes. This reflects our expectation, based on the known low conductivity of the encapsulant, that the surfaces are likely not to be at a uniform temperature (not isothermal). The relative sizes of inner and outer nodes can significantly affect the quality of the model.

Figure 12: DELPHI compact model produced by FLOPACK for a 256-lead 28×28mm PQFP

DELPHI compact model produced by FLOPACK for a 256-lead 28×28mm PQFP

Engineers working with spreadsheets, or other simplified methods, will probably prefer to use a two-resistor model, calculating separately the heat transferred to the board and through the outside of the package to the ambient. Those fortunate enough to have a thermal modelling package have more choice, but must be careful which models they choose, since these will affect both the accuracy of the calculation and the time taken for computation.

To think about

The two-resistor and DELPHI models are not the only possibilities. For example, Gerstenmaier and his colleagues (Boundary independent exact thermal model for electronic systems – PDF file, 776KB) worked to create a compact thermal model describing the junction temperatures and heat flows of packages. Their work led to a systematic way of constructing thermal resistor networks for a number of contact areas and heat sources. The parameters are determined by successive linear fits between simulated and measured temperatures and heat flows within the system.

This work was extended further in work by Bosch and Sabry (Thermal compact models for electronic systems – PDF file, 283KB), who comment that many compact thermal models suffer from the need to make ad hoc assumptions about the number of nodes to be used, and also require a pre-determined set of boundary conditions used to generate the model. By contrast, their work aimed to improve the mathematical rigour and establish the model on a better understanding of the physics involved. The fundamental difference between their approach and the DELPHI method is that, for DELPHI, a model is found that corresponds to a heat flux distribution that is unknown. The advantage of using a known distribution corresponding to the compact model is that error estimates are more easily available.

Their analysis claims the advantage that adding extra nodes only complicates the size of the matrix, and the computing complexity increases only linearly with the number of degrees of freedom, whereas optimisation becomes progressively more difficult when generating compact models in many ways. Further, their proposed method has proven to work for components with multiple heat sources.


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Validating the models

Thermal parameters can be calculated from a model of the physical component, assuming that sufficient information is available. However, materials in particular are quite variable in their performance, so most users prefer parameters measured on representative devices. In the traditional JEDEC methodology, modelling is validated against the results of standard tests (Figure 13).

Figure 13: Validation model for JEDEC thermal parameters

Validation model for JEDEC thermal parameters


The DELPHI workers developed an alternative methodology by which their detailed model could be refined and validated, but in which testing has a subordinate role:

Figure 14: Validation procedure for DELPHI thermal models

Validation procedure for DELPHI thermal models



Read Shidore and Sahrapour DELPHI Compact Models Revolutionize Thermal Design for an insight into the way that DELPHI models are created and validated, and into the magnitude of typical inaccuracies.


How accurate are our models? As so often in thermal management, “It all depends . . . ”. DeVoe and Ortega5 compared simulation with measurement on a board with a wide range of conductivities and exposed to a wide variety of convection cooling conditions. They found that the ability of a compact model to predict conditions compared with a fully-detailed package depended on whether or not there were strong local temperature gradients on the board. With a highly conducting board (K=100W/mK), the high conductivity smooths out local board temperature gradients and the thermal models were accurate, even though the board heat flow path is dominant. For intermediate conductivities, the heat conduction is still significant, but the conductivity is low enough to allow significant temperature gradients across the board. These conditions made the compact thermal model a much worse predictor of reality.

5 DeVoe and Ortega An investigation of board level effects on compact thermal models of electronic chip packages


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Responsibility for the models

The inspiration for the DELPHI project in developing a generic thermal model was claimed (DPAC News, Spring 1998) to have been drawn from the following quotation from Bar-Cohen, Elperan and Eliasi: “The thermal precision required in the development of a competitive packaging design could best be served by vendor delivery of a validated numerical model . . . for each chip package in its inventory.” And we have already seen that one of the project deliverables was a definition of the boundary separating the ‘thermal responsibilities’ of the manufacturer from the customer. Creating a detailed model, and deriving from this a validated compact model, meets these obligations, provided that the user has a clear idea of how to use the model. and of any limitations and assumptions.


In March 2003, Bruce Guenin started his update on thermal standards work by JC15.1 with a definition of a paradigm as “A set of assumptions, concepts, values and practices that constitute a way of viewing reality for the community that shares them, especially in an intellectual discipline.” He noted further that the term can be applied in other contexts, and sometimes is used more loosely to mean “the prevailing view of things”.

In the ‘old paradigm’ the customer ordered it and the supplier shipped it, with the supplier characterising the product, but recommending that the customer should re-do the work. Guenin contrasted this with the ‘new paradigm’, where the part is characterised by the supplier, who provides the customer with a set of data that will support all engineering functions involving the product.

Hey buddy, can you spare a paradigm? (PDF file, 1.15MB)


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Further reading on modelling


“Component modelling is one of the most difficult issues in thermal design . . . a great difficulty is that the subject is deceiving. It may at first glance seem simple but once all its intricate details have been unfolded this appearance changes drastically.”

Åke Mälhammar, Thermal Component Models, part 1


For reasons of length, our text has inevitably been somewhat simplified. There is much more to read about this subject, and some articles are very heavy going! We have already included some references to web-based materials, but we have suggested below extra approachable resources that you would benefit from exploring in order to expand your knowledge of what is a major topic. You may also find them useful in preparing a considered answer to one of the sections of Assignment 1.

Further reading

Åke Mälhammar’s series of articles Thermal Component Models, previously available at CoolingZone, but now archived at these links (Part 1; Part 2; Part 3), and Thermal Component Models and Accuracy Windows

Bruce Guenin’s series of articles Determining the junction temperature in a plastic semiconductor package, available at Electronics Cooling at these links: part 1; part 2; part 3 (the use of the junction-to-board thermal characterization parameter); part 4 (localized heat generation on the die), and his tutorial The Use of Spreadsheets in Packaging Thermal Calculations (archived PDF file, 962k)


Recommended viewing

As one of our resources for this module, we are making available a presentation that one of the course authors made to a group of engineers attending a one-day awareness seminar. In this session, which was given before the session that we recommended as part of Unit 11, Murray MacCallum is describing the thermal modelling challenge and the differences between the different types of model. The presentation has been “tidied up” very little, and it’s very much a live event, including some “noises off”, so we haven’t provided a script. However, all the basic information you need is in this Unit text.


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Transient conditions

So far in our discussion we have implied that the values of thermal resistances and characterisation parameters measured or estimated relate to steady-state conditions. However, the real world is not always steady-state, and you may have noticed that the JESD standards also describe transient measurements and that the FLOTHERM tools also allow for transient analysis. Whilst transients are often avoided on account of their complexity and greatly increased computational requirements, we cannot ignore them; not only do devices have different characteristics when operated under transient conditions, but measuring what happens when a pulse of power arrives at a junction can give valuable insight into the thermal structure of a device.

Power dissipation limits

All power semiconductors have a power dissipation limitation. For rectifier products, with a well-defined on-state voltage drop, this can easily be translated into terms of current ratings. However, transistors are more complicated, because they can operate in the on state at any voltage up to their maximum rating, depending on circuit conditions. It is therefore necessary to specify a safe operating area (SOA) for transistors which specifies the power dissipation limit in terms of a series of boundaries in the current and voltage plane. These are usually given for mounting base temperatures of 25°C, and need to be reduced for higher temperatures.

When a device is subjected to pulsed power, a higher peak power dissipation is allowed. This is because the materials of the device have at least some thermal capacity, and the critical junction temperature will not be reached instantaneously, even though excessive power is being dissipated. The extension of the power dissipation limit will depend on the duration of the pulse and the duty factor, which reflects the frequency with which the pulse recurs.

If power is applied to a device, it will immediately start to warm up. If the power dissipation continues, then a balance will be struck between heat generation and heat removal, resulting in the junction stabilising at the “steady state” temperature, determined by the thermal resistance associated with the device and its thermal environment.

Some heat energy will be stored by the thermal capacity, so that the device will not just lose temperature immediately if the power dissipation ceases, the rate of cooling being identical to the rate at which heating took place.

However, if power dissipation ceases before the temperature is stabilised, the peak value will be less than for continuous power dissipation. If further pulses of power are applied, and cooling has not been allowed to be completed, the peak temperature obtained by the end of each successive pulse will be greater than that at the end of the pulse before, and succeeding pulses will build up the temperature until a new stable situation is obtained (Figure 15).

Figure 15: A train of power pulses increases the average temperature if the device does not have time to cool between pulses

A train of power pulses increases the average temperature if the device does not have time to cool between pulses


The temperature of the device in this stable condition will fluctuate above and below the mean, so the life expectancy of the device may be reduced should the upward excursion extend beyond the permitted junction temperature. This can happen with high-power low-duty factor pulses, even though the average power is below the DC rating of the device.

Supplementary information

Rick Cory’s article PIN-limited diode effectively protect receivers (PDF file, 325KB) is not only interesting from the point of view of preventing electronic damage, but its information on the thermal characteristics of the PIN diode includes a demonstration of the way in which devices can withstand isolated pulses much more readily than repeated pulses, as the latter cause a general upward drift in both mean and peak temperatures. There is no problem if the device has time to ‘recover’ after the burst of energy, but applying longer pulses of power and increasing the duty cycle both increase the maximum temperature. Note how important it is to have a working estimate of the thermal time constant of the device. In this case it is very low (only 46µs); other structures will have significantly longer thermal time constants, but the same general principles apply.

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Using transient measurements to determine device characteristics

In this section, we have made brief notes on three papers which we would encourage you to read in their entirety.

In An alternative approach to junction-to-case thermal resistance measurements, Bernie Siegal makes the point that thermal parameter measurements are difficult to make because of the problem of mounting a temperature-measuring device (such as a thermocouple) without the thermal situation being distorted by the mass of the thermocouple and the space it takes up.

He proposed an alternative approach, based on measuring the time taken for heat to propagate from its source at the semiconductor junction to the outer surface of the package. The best way to see this is to use a ‘heating curve’, which shows TJ (or something proportional to it) as a function of the time for which power has been applied. The time axis used for heating curves is usually logarithmic, to reflect the fast initial heating and the slow approach to steady-state conditions.

The temperature of the junction will start at TA, and rise as a function of time; at the point when the heat has just reached the package boundary, the surface will be isothermal and the boundary condition at the surface will have no effect. However, as heat continues to be generated for longer than the propagation time to the surface, the shape of the curve will change, depending on the applied boundary conditions, which will determine the ultimate value of TJ, as shown in Figure 16. Here the heating time, tH, at which the curves start to diverge is of the order of 1.5s.

Figure 16: Typical heating curves generated for a thermally-enhanced BGA package mounted on a JEDEC high thermal conductivity thermal test board

Typical heating curves generated for a thermally-enhanced BGA package mounted on a JEDEC high thermal conductivity thermal test board

Source: B. Siegel, op.cit.

In Dynamic temperature measurements: Tools providing a look into package and mount structures, Poppe and Székely show how the approach can be extended to help in the modelling of the response of an assembly to heat transients, adding the thermal equivalent of capacitance to the model (Figure 17).

Figure 17: The build-up of thermal resistance and its analogue as an R-C network

The build-up of thermal resistance and its analogue as an R-C network

Source: Poppe and Székely, op.cit.

The discontinuities in the heating curve give insights into the performance of the materials from which the assembly is made and the interfaces between them. There is more about the contribution of the different layers in Clemens Lasance, Dynamic measurements: A cornerstone of the European PROFIT project; Figure 18 shows a temperature-time response curve that has been mathematically transformed into a curve that distinguishes the various parts of the component. The horizontal axis shows the thermal resistance, from left to right, going from the junction to the ambient; the vertical axis is related to the cross-sectional area of the heat flow path. The distance between the maxima of the curve provides information about the thermal resistance of distinct parts of the package.

Figure 18: The differential structure function for an Intel processor, showing various package characteristics

The differential structure function for an Intel processor, showing various package characteristics

Source: C. Lasance, op.cit.

Lasance also demonstrates how the performance of interfaces may be measured, and even used as an element in manufacturing quality control (Figure 19).

Figure 19: Differences between processed temperature responses indicating die attach failure

Differences between processed temperature responses indicating die attach failure

Source: C. Lasance, op.cit.

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Other types of component

Assouad6 and his colleagues applied the DELPHI methodology to a range of transformers. They point out that transformers are critical from the thermal point of view because high temperatures can result in reduced performance:

Their work was complicated by differences in the winding materials (foils and Litz wire, as well as standard copper wire) and the fact that the materials can be anisotropic. The dual cold plate method is difficult to apply to a transformer, so they set the boundary using a fluid bath. Because the heat transfer coefficient within the fluid is different at different temperatures, this had to be measured using a metal dummy and examining the temperature distribution. A further complication was that an integrated circuit has a single heat source, whereas a transformer has several heat sources, the windings and the core. To accommodate this the simulation was run twice, and the two models ‘added together’ using the principle of superposition described in Unit 4.

6 Assouad et al. Thermal characterization and modelling of EFD transformers, applying DELPHI methodology (PDF file, 372KB)


Multiple heat sources

The issue of multiple thermal sources is also addressed in a paper by Lall7, where a number of devices packed in a single plastic multi-chip module. Again the concept of superposition of temperatures was used, in conjunction with the idea of a chip-location-specific junction-to-package thermal resistance that was defined in terms of the local power dissipation at the chip. Lall and his colleagues also used the concept of ‘adiabatic temperature’, that is the equilibrium temperature achieved by a component on the board in the absence of self heating, but taking into account the heating of the package due to neighbouring chips. This creates a reference temperature for defining the heat transfer coefficient in convective cooling.

7 B. S. Lall, B. M. Guenin, and R. J. Molnar, Methodology for Thermal Evaluation of Multichip Modules, IEEE Trans. Comp., Packaging, Manuf. Technol. (PDF file, 202KB)


Figure 20 shows a thermal resistance network devised and verified by the Amkor team for a multiple chip package; in this case the part had four chips mounted within it, and a series of tests carried out in natural convection, powered these devices separately in order to verify the application of the superposition theory. Using this approach allowed a model to be created that worked well, even where the devices were not powered equally.

Figure 20: Thermal resistor network for lateral-chip MCM

Thermal resistor network for lateral-chip MCM

Source: Bruce Guenin, Thermal Calculations for Multi-chip Modules

Supplementary information

In Characterizing a package on a populated printed circuit board Bruce Guenin extends the idea of multiple heat sources and superposition to a PCB.


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Tools for component modelling

Theoretically it would be possible to build up an exact physical model of each component within the thermal modelling package, assign the appropriate material parameters, and let the programme compute the heat flow in detail. Apart from the computation involved, and the time this might take, there is also some danger that the model may not represent the real component – the modelling technique, the accuracy of the detail, and variations in materials may all contribute to this. For this reason, most packages will use a simplified representation of the component provided by the device manufacturer or calculated using one of the specialised tools available.


FLOPACK is an example of such a tool, providing both two-resistor and DELPHI models. The FLOPACK approach pulls together design information from both manufacturer and user, aiming to generate a “reasonably accurate package model from a reduced set of input parameters”. So the user has only to input a minimum of data, and FLOPACK does the “hard work in making intelligent guesses from the rest of the information on the design sheet”. Definitely an approach to appeal to system designers!

Whilst the programme is sufficiently intelligent to make assumptions about the internal assembly of standard packages, this is not a limitation, because the user is able to adjust the physical model in line with the internal design and materials used. A flavour of this can be gained by going through this FLOPACK walkthrough. Notice the degree of detail used internally by the calculation, and the relative simplicity of the models that result. Dividing the task in this way is an important contributor to computational efficiency. At the same time, if the model is produced by the component supplier, it may be verified against measurements under standard conditions, and adjusted for best accuracy.

The models created may be either detailed or compact, the latter being available in both two-resistor and DELPHI forms. The two-resistor models are computationally efficient, and are claimed to predict junction temperatures that are accurate to 30% worst case:“Two-resistor models are a major improvement over traditional single-resistor metrics such as junction-to-ambient resistance ΘJA, which have been shown to be inaccurate to 60% or more”. The DELPHI compact models are claimed to be a significant improvement over two-resistor models, yet will produce a very similar prediction to the detailed model for most environments, whilst greatly reducing simulation time.


SmartParts3D ( is a free resource for the electronics design professional that will eventually be able to streamline the process of collecting physical design information from multiple suppliers. Funded by “Partnership in Design”, a supplier group, the aim is to help members deliver information about their products in an interactive and cost-effective manner. It is well worth keeping an eye on this initiative, as it is potentially very valuable, although the current store of information lacks breadth.

Go through this SmartParts walkthrough to gain an overview of how the resource works.

The models

The starting point is a mechanical description of the package, simplified as far as possible, and modelling the key structural elements as cuboidal blocks7 with appropriate values of thermal conductivity. Figure 21, which is an animation that sequentially highlights the important areas, shows the degree of simplification involved.

7 The use of rectilinear coordinates and cuboid cells is a limitation due to the Flomerics philosophy – other software will allow more accurate meshing and radiused surfaces. However, as far as conduction is concerned, these effects are second order.

Figure 21: Animated view of simplified package model used for generating thermal parameters

Animated view of simplified package model used for generating thermal parameters


When viewed within FLOTHERM, the tree structure shown in Figure 22 can be used to steer around the package and identify the element of the device under review.

Figure 22: Expanded tree structure in FLOTHERM, showing the component build-up

Expanded tree structure in FLOTHERM, showing the component build-up ""


Each of the elements can be associated with an internally generated power and thermal characteristics, so that it is relatively easy to make modifications for different lead-frame designs and materials. Notice that, although fairly detailed, there are simplifications used to simplify the computation. For example, the heat is treated as generated over the whole surface area of the die. If this is not the case, then the die needs to be ‘exploded’ and itself built up as a model, using the silicon parameters for thermal conduction – not for the faint-hearted.

Supplementary information

Details on FLOPACK are available at, and you will be using this tool as part of Assignment 1. Walkthrough 8 (Compact vs detailed component models) shows you how to use the tool.


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Resources for this Unit

Each of these lists is in the order in which the material is referenced in the Unit text. However, note that links to the SAQ answer is not included!

Needed for activities

Recommended supplementary material

Optional links and information

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