Board fabrication is a relatively complex batch process with many stages, and a range of process options and alternative methods which enable the fabricator to offer a “kit bag” of solutions to the designer. Working as a team, fabricator and designer are able to choose the most appropriate solution for the task in hand, bearing in mind both the requirements of the end-customer and the limitations of the process.
This team effort continues at the manufacturing stage because inherent in the fabrication processes are changes to dimensions that need to be compensated for by the fabricator. The user may demand a specific track width and dielectric thickness, and creates a design for that, but the fabricator has to start from a different base, modifying artwork and setting process parameters that will produce the required final result. Which is why in Unit 8 we will be looking at the work carried out by the fabricator’s front-end engineering team.
But at this stage of your studies, the aim is to look at the process sequences used and each of the fabrication processes in some detail. Of course, we have already considered plating as a generic enabling process in Unit 2, and many of the materials aspects have been captured in Unit 1. So this unit starts with the process sequences, adding more detail to the outline that you may have glanced at when reading the module introduction. We then take each of the processes in the sequence used in a typical multilayer board, before considering key aspects of board quality.
The PCB manufacturing process starts with the ‘process blank’, a large sheet of laminate which will be divided after processing into individual circuits or panels containing multiples of circuits. In order to minimise the area of laminate which is wasted, care has to be taken in selecting the size of blank and the arrangement of the panels on the blank. This is a critical area for cost minimisation, and will be considered in more detail in Unit 8.
There are two main board patterning options which may be used alone or in combination to create any type of PCB:
In a fully additive process, the base laminate would start without a copper covering, and the copper for the tracks be deposited only where needed. This gives, in theory at least, potential for considerable cost and environmental savings, but the processes are complex, and totally additive processes have not yet become common.
However, some additive element is needed to create connections between layers, as the inside of a drilled hole necessarily starts free of copper! Most boards are therefore made using what is referred to as a ‘semi-additive’ process, where the starting point is a thin copper-clad laminate, with holes which are plated internally (additive) and surface patterns which are etched (subtractive).
The following sections look first at the way in which these two options are used to create PCBs, before giving further information on the techniques involved.
Single-sided boards can be made by a very simple subtractive process, using clad copper laminate as the base material. Etch resist is applied to the board to protect the required pattern, following which an etchant is used to dissolve the copper that is not needed, leaving behind a track pattern and component lands firmly adhered to the surface of the base material.
The main elements of a typical process sequence for a simple single-sided board are:
|1||Screen print liquid etch resist and cure|
|2||Etch exposed copper areas (that is, those not protected by resist)|
|4||Screen print solder mask|
|5||Screen print component identification (‘legend’ or ‘nomenclature’)|
|6||Apply solderable finish|
|7||Drill or punch component holes|
|8||Visual inspection and (optional) electrical test|
Depending on the design requirements, Steps 4, 5 and 6 may be omitted.
The technique of applying etch resist is also called ‘print and etch’, and was the process which gave rise to the ‘printed’ in ‘printed circuit board’: the board produced is sometimes termed a ‘conventional’ board. Screen printing generally produces boards of only limited accuracy and quality, so a photographic image transfer technique is used for high-density PCBs. The process route given in Table 2 describes the process both for ‘conventional’ boards, produced by screen printing, and the more accurate types produced by photoresist techniques – note that PCBs with finer features generally demand more inspection and test, even for single-sided boards.
|Non-critical circuits||Boards with finer feature|
Cut, edge and clean panels
|Screen print positive liquid etch resist and UV cure||Laminate with dry film resist, image and develop|
Etch exposed copper areas not protected by primary resist
Strip primary resist
Brush clean copper pattern
|Screen print solder mask||AOI scan|
|Apply, expose and develop photoimageable solder mask|
Screen print component indent
Apply solderable finish (HASL, nickel-gold, immersion tin/silver)
NC drill or punch component holes
Trim board to final size required
Electrical test (if specified)
Final visual inspection
Printing can also be used to make double-sided boards, with a double application of resist, and a single etching step. However, in order to improve the alignment between the patterns on opposite sides, photoresist methods are generally preferred, with simultaneous exposure to ultra-violet light, placing the board between a pair of photomasks which have been accurately aligned to each other.
Double-sided boards without plated through-holes are rarely a product in themselves, because they lead to assembly problems and have unreliability consequences: when pins or components leads are used to join the two sides, flux and air are trapped inside the hole, resulting in poor joints. However, such double-sided boards, generally without holes and made with a very thin laminate, form the ‘inner layers’ or ‘cores’ from which multilayer constructions are made.
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Board manufacture generally involves some processes which add copper both to conductive areas and the inside of holes. Regardless of which process is used for plating, when patterning is intended, there are two alternative approaches referred to in the industry. These are:
Panel plating and pattern plating may be carried out either by electrolytic or electroless processes, depending on the material to be deposited and on whether any parts of the area are not already covered by a conductive layer.
As may be seen in Figure 1, there are obvious differences between the approaches in terms of the definition and accuracy of the copper pattern produced.
Note that the pattern plating process still needs an etch after patterning, in order to remove the base metallisation or foil.
Explain the way in which subtractive and additive processes can be combined in the manufacture of PTH boards.
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The most common manufacturing route for plated through-hole boards uses a plating of tin (formerly tin-lead) as a solder resist after electroless plating copper overall:
|1||Cut, edge and clean panels|
|2||NC drill all holes|
|4||De-smear and electroless1 copper plate all exposed surfaces|
|5||Clean board surfaces and laminate primary dry film resist|
|6||Expose and develop dry film|
|7||Electroplate approx. 25 µm of copper and 4-10 µm of tin|
|8||Strip primary resist|
|9||Etch exposed areas of copper|
|10||Strip tin deposit|
|11||Brush clean copper pattern|
|12||AOI scan if high density|
|13||Apply photoimageable solder mask and dry|
|14||Expose and develop solder mask|
|15||Screen print any component identification|
|16||Apply solderable finish (e.g. HASL, electroless nickel-gold)|
|17||Trim board to final size required|
|19||Final visual inspection|
Depending on the design requirements, Step 15 may be omitted.
With a single-sided board, the crossovers that any real circuit requires have to be provided by the components acting as ‘bridges’. With a second copper pattern on a double-sided board, there is additional freedom. However, as soon as tracking gets complicated, and especially with shrinking component sizes, two layers of interconnect are insufficient, however fine the patterning. There is also competition for space on the foil layer from the relatively wide connections needed to give low-impedance paths for power and ground.
The inevitable consequence was the early development of the multilayer printed circuit board, where a composite is built by laminating together pre-patterned boards. Early problems associated with lamination failure have long been resolved, and the resulting multilayer board is the workhorse of the industry. In most applications, at least two of the layers (usually internal) are dedicated to power and ground distribution, and are essentially complete planes of copper with isolation holes for through connections, and the whole of the remaining ‘signal’ layers are available for interconnection
The final stages of processing multilayer boards are the same as for plated through-hole boards, but what is processed is a ‘sandwich’ of pre-patterned double-sided boards between two blank sheets of single-sided laminate or, more usually, two copper foils. The sandwich is held together, and the layers of foil insulated from each other, by interleaving sheets of ‘prepreg’. Prepreg consists of thin sheets of glass fabric impregnated with epoxy resin which has been only partially cured – so-called ‘B-stage’.
The inner layers, outer foils and prepreg are carefully assembled (a process referred to as lay-up) and heat and pressure are applied to create a single composite laminate, completing the curing process of the epoxy resin.
Inner layers are not visible from the surface, so that it is very important to make sure that these are correct before lay-up to form the multilayer assembly. This is always done visually, in order to avoid damage, usually involving Automated Optical Inspection (AOI) equipment. Depending on the quality constraints, it may be possible to carry out some degree of repair of defective inner layers, but only before lamination.
In order to get the best possible yield, these ‘inner layers’ have their metal surfaces treated in order to improve adhesion. A number of processes are used for this, the traditional ‘black copper’ process, which builds up a layer of oxide on the copper, now being under threat for environmental reasons. After the surface treatment, the inner layers must be handled very carefully.
The multilayer process sequence is given in Table 4. Note that Steps 1 to 8 need to be repeated for each of the inner cores: a six-layer board will be made from two double-sided cores and two copper foils or outer boards, and involve a total of three double-sided patterning processes.
|1||Cut and clean inner layer cores|
|2||Laminate primary dry film resist|
|3||Expose and develop dry film|
|4||Etch exposed areas of copper (acid or ammoniacal etchant)|
|5||Strip primary resist2|
|6||Post-etch punch registration slots|
|7||AOI scan inner layers|
|8||Surface treat the copper to enhance adhesion (‘black oxide’)|
|9||‘Lay-up inner layers’ with prepreg and outer layer copper foils|
|11||Remove resin spew and clean panel edges|
|12||Post-bond tool NC drill registration holes (located with reference to inner layers)|
|13||Process as PTH board|
The many process steps in making a multilayer board, and the increased opportunity for defects, mean that much attention has to be paid to in-process quality control. Even with this, a multilayer construction is substantially more expensive than double-sided PTH, and the cost increases dramatically with layer count, because of both complexity and reduced yield. Multilayer boards have been made with over thirty layers, but boards with four to twelve layers are most common.
Explain the way in which inner layers are inspected and treated, and the reasons for this.
The PCB fabricator is typically an independent operation, providing a custom product for a range of discerning customers. The nature of the business is that quantities are very variable, from a few-off prototypes to high volume, but they share the challenge that each design is specific to its application. This means that little preparatory work can be done, except procurement of materials, and an order has to be fulfilled by starting one or more batches and taking them all the way through the production process.
The nature of the processes is that some use of conveyors between stages is possible, such as between exposure, development, etch and strip, but process blanks and panels are typically handled in batches using cassettes. Conveyors are typically of the brush or roller variety, and capable of handling a range of sizes. In contrast to those that you will see in an assembly environment, most board conveyors are not involved in the alignment process, so do not have to be adjusted between batches.
Mechanisation within the plating areas is dictated by the need to make good electrical contact with the board. Plating processes involve immersion in a succession of baths, which is carried out by automated handlers with a fair degree of flexibility and intelligence.
The turn-round on the entire process will depend on volume, but may be as low as a few days at the prototype stage. In fact, some companies are able to produce even quite sophisticated boards in less than 72 hours. Commercially there is always a significant premium for fast turn-round batches, as these will have to take priority over other production throughout the process sequence.
The combined consequence of batch operation, of yields that are always less than 100 per cent, and of the customer’s need to have a defined number of boards, particularly at the prototype stage, is that most companies slightly over-make, and will retain surplus boards for subsequent sale. However, storage limitations frequently mean that surplus parts, and even master artwork, may only be retained for as little as six months.
The PCB factory is typically quite large, and has a number of processes with safety implications. Moving machinery, as in drills, are obvious hazards, but these are easily guarded, and the main safety issues relate to the chemical processes. Even copper plating involves sulphuric acid (a hazard to people) and a copper salt which is fairly poisonous, and the copper itself (classed as a ‘heavy metal’) is hazardous waste. Be aware that major costs are incurred by the PCB manufacturing industry in meeting the requirements for effective and environmentally-friendly effluent disposal.
More about these environmental concerns and costs in Board fabrication issues.
The starting points for the fabricator are laminated foil, prepreg, chemicals and photographic materials, all of which are purchased. You already have some information on laminate, foil and prepreg from Unit 1: photographic materials are a commodity item, but be aware that the chemicals used are not straightforward chemicals that one might buy from a laboratory supplier. Specialist suppliers have made a very significant investment in producing groups of chemicals and other materials for the processes involved, and these proprietary items are not interchangeable – each board fabricator you contact will have made different decisions about the specific materials used, and these may have significant implications for the quality and reliability of the end product. The most significant differences will be found between materials intended for electroless plating.
As was pointed out in the introductory Fabrication and assembly process outline, you need to have a very firm grasp of fabrication sequences for the main types of boards. If you have not done this earlier, we recommend that you do some browsing to establish the process flows used by typical manufacturers. As an example, you can take the plant tour at Proto Engineering, which will show you the kind of equipment used. If you are looking for a starting point, there are some nice long lists of fabricators and assemblers at Surfinbox.
We recommend that you don’t be seduced by the pretty pictures, but try and generate flow diagrams showing the sequence of process steps. Hopefully there will be many similarities between different companies! You should, however, expect there to be some differences, reflecting whether the company’s primary focus is in prototyping or in volume production. There will certainly be differences in the materials used.
Comparing our process flow sequences against real life should also illustrate that most companies introduce more QA stages than our simplified outline. This helps protect yield as well as ensuring satisfactory overall quality.
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In the first part of this unit we concentrated on the sequence of processes: the aim now is to give you more understanding of the processes themselves.
As you read this section, please think about the process sequence and be sure you know where the process is used within board manufacture. We have tried as far as possible to describe the processes in the sequence experienced by a typical board, but there can be some variation, depending on the exact process used. Knowing the normal sequences will also greatly help you when you visit a factory, because the physical arrangement of many factories does not mirror the process sequence.
The need for cleaning arises because process blanks may easily get contaminated during storage and handling. Oils and acids from finger grease, for example, can have a deleterious effect on subsequent processing, and dust and other deposits also need to be removed if high yield is to be obtained.
The board cleaning operation is vital to board quality, because the adhesion of the photosensitive films and resists is essential to produce well-defined copper features. The process needs both to remove the thin layer of surface oxide on the copper, and roughen the surface slightly. Three ways of cleaning are used, the first two of which are mechanical scrubbing methods:
Brush scrubbing or ‘standard brushing’, uses rotating wet brushes with abrasive particles. Brush scrubbing tends to impart stress to a thin core material by deforming it, so its use is normally restricted to cleaning outer layers. Brush scrubbing can also produce a surface that is not compatible with fine-line circuit designs.
Pumice scrubbing, using brush or jet, is becoming more common because it creates minimal distortion and most high technology pumice machines will scrub cores down to 0.1 mm thick. Pumice, a volcanic material, starts as a solid foam whose pores are made of very thin layers of a glass that is hard and resistant to chemical attack and consists mainly of silica. The pumice is powdered and formulated into a slightly acidic slurry. Mechanical movement of the slurry across the copper surface removes a thin uniform layer of oxide and copper, whilst the action of the pumice particles creates a microscopically rough surface of virgin copper.
Chemical cleaning, using a micro-etch) is normally chosen for cores less than 0.1 mm thick and for materials with coarse weave patterns (such as PTFE).
An alternative which is gaining in popularity is to avoid cleaning altogether by specifying ‘reverse-treated’3 foils, which do not require surface preparation because they have rough surfaces on both sides. The processes are proprietary but complex – details of this type of product can be found at http://www.gouldelectronics.com/ under RTC.
3 The Gould web site says that “Reverse-treated copper foil is manufactured by applying copper nodularization, brass thermal barrier and passivation to the shiny smooth side of the foil rather than to the roughened matte side of the foil as is done when manufacturing conventional or standard copper foil. A thin layer containing only passivation or antioxidants, which is normally applied to the shiny smooth side of standard foils, is applied to the roughened matte side of reverse treated foil. The fully treated side is laminated to a prepreg leaving the roughened matte side of reverse treated foil available for inner-layer processing.”
For single-sided boards, and the majority of PTH and multilayer applications, drilling is carried out by mechanical means, using tungsten carbide-tipped drills. The need to drill fast and accurately with minimal drill smear has prompted much research work in the design of drill bits, drill entry conditions, and drilling spindles. Although now a very highly mechanised process, hole drilling is still usually the largest single component of board cost. CNC drilling machines have been developed to give:
Drilling is a one-at-a-time process, and punching is a substantially cheaper alternative, especially where this can be combined with profiling, thus removing the need for routing. Punching is, however, only practicable when:
As the paper-phenolic laminates associated with low-cost applications can be processed in this way, punching is most commonly seen with simple single-sided and double-sided boards.
Double-sided boards are drilled before patterning, so the absolute location of the holes is not important, provided that tooling holes for locating the phototool on the panel are drilled at the same time, and that the relative position of the holes is within tolerance. This means that relatively crude jigging can be used, and allows drilling of a stack of blanks to a depth of approximately five times the drill bit diameter.
By contrast, multilayer boards have patterns imaged on the inner layers, and the drilling positions must match these exactly. Three methods are used to provide accurate hole location:
‘Soft plug tooling’: Tooling holes are pre-punched in the panels, and used first to align the exposure artwork, and then to locate the panel in the drilling machine. The tooling plate on the machine has areas in which replaceable plugs of brass or nylon can be inserted. These are drilled with the actual drill spindle used for drilling the circuit board, to provide exact spindle to tooling location. Tooling pins are then pressed into these holes, and the panels are loaded over these pins.
Post-etch punch registration: Four slots for drill machine positioning are punched, referenced to fiducials on the panel, but taking into account the stretch factors electronically introduced into the laser-plotted phototools. This accommodates the shrinkage (primarily in the warp direction) during the pressing operation.
X-ray registration: Two tooling holes are drilled, precisely referenced to the internal circuit image using X-ray positioning. Panels can then be pinned together and handled as double-sided boards.
Most multilayer boards currently use post-etch punch registration.
Thin sheets of aluminium, aluminium-clad composite or phenolic-paper laminate are placed both on top of and below the stack. The ‘entry material’, 150–500µm thick, is designed to protect the top panel surface from damage and burrs, centre the bit to prevent deflection, and lower the impact on the bit to minimise breakage; ‘backup material’, 1.6–3.2mm thick, gives the drill bit “somewhere to go”, and minimises burrs on the exit surface. Once used, the sheets will generally be discarded, but may be recycled, depending on the choice of material.
The standard drill for larger holes is made of wear-resistant tungsten carbide crystals cemented in a cobalt binder. However, once drill diameters reduce below 0.5mm, there are problems of drill breakage on removal, and an increase in scrap due to poor hole location. Increasing the percentage of binder makes the drill less likely to break, but more prone to wear and likely to deflect more during drilling. With a standard hard high tungsten carbide content drill, improvements have been reported from using a friction-reducing surface coating of carbon, deposited as a diamond-like film by chemical vapour deposition (CVD).
Drilling can typically account for 20% of the unit cost of a standard multilayer. However, the long-term trend has been towards high density designs with increased use of smaller and smaller via holes, in order to minimise the use of board ‘real estate’. This implies lower stack heights and a resultant significant cost increase.
The practicable limit for drilled holes is around 0.30mm, below which the drill bits become very fragile. For small vias, etching and plasma techniques are sometimes used, but ‘laser ablation’ is the alternative to drilling which is finding favour, especially for blind vias. Focused laser energy is repeatedly pulsed at the material to be drilled, vaporising layer after layer until a hole is created. High pulse power, combined with low average power, allows material to be removed without the organic materials in the board burning and leaving a carbon residue.
There are two main types of laser in use:
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As you will recall from Tables 3 and 4, a great deal of patterning takes place when making a multilayer board – each of the internal layers is first patterned on both sides, using a dry film resist, and finally so is the pressed multilayer. It is only at the pressed multilayer stage that drilling is used, with appropriate precautions to ensure alignment to the inner layers, and a combination of electroless plating and electroplating is used to plate the walls of the holes with a ductile coating of copper that will withstand temperature cycling. Again, the basic procedures have been described in Unit 2.
However, our description has been of the most common type of board, which contains only through vias. Where blind vias are needed, creating connections hidden inside the board, then the drilling and plating processes used for through-hole fabrication need also to be applied at the core level. The additional complexity can be expected to add to the price!
All the processes involved demand careful control, because it is not possible to repair inner layers after lamination. For this reason, it is common practice before lamination to use Automated Optical Inspection (AOI) on inner layers in order to maximise yield. Depending on the customer specification, a limited amount of rework is allowable at this stage.
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Before the multilayer assembly is laid up for lamination, each internal copper surface is chemically treated in order to promote good adhesion to the prepreg. One previously common process is referred to either as ‘black oxide’ or ‘brown oxide’. In this, controlled oxidation forms a thin layer of oxide, which both increases the surface area and reduces the reactivity of the copper, passivating the copper surface. The quality of the bond obtained depends on the ratio of cuprous to cupric oxide, and on properties such as the growth rate and porosity of the layer.
When the oxide process has been incorrectly carried out, the panel can be stripped and re-coated. However, the more process cycles, the higher the possibility of salts or etchant residues remaining after rinsing, which can cause poor lamination or subsequent failure in reflow soldering. There is also a marginal effect on copper thickness, as each pass removes 1–2 µm of copper, but this is within the foil thickness tolerance, and should not effect the functionality of even controlled-impedance boards.
Probably a preferred alternative to this oxide process is a modified micro-etch. In this, the foil surface remains metallic copper, but its area and roughness are both increased, to enhance adhesion with the prepreg resin.
Prepreg sheets are used between the ‘cores’ to provide both dielectric spacing and adhesion. A prepreg is a woven glass fibre mat that has been coated with resin and only partly polymerised, to leave the resin as a ‘Stage B’ material. Prepregs come in a range of standard types to give different bond thicknesses and finishes. It has been common practice to use two prepregs between layers, in order to . Special prepregs are used for bonding heat sink to boards. No-flow and low-flow types have also been developed for use in flex-rigid board manufacture.
Inner layer cores, prepregs and outer layer copper foils are laid-up between press and liner (‘caul’) plates to fill a press ‘daylight’. Standard 1.6 mm thick 4-layer boards would typically be pressed eight-high in one daylight, the board elements being held in correct registration by pinning or equivalent tooling. Liner plates help to give a uniform distribution of heat and pressure.
A conventional hot transfer vacuum press takes around one hour for the hot press cycle, at a temperature of approx. 180°C for FR-4 material. More boards are now being bonded in autoclave presses which have a longer press cycle (3–4 hours) but much greater capacities and flexibility over panel sizes.
One process control used for the lamination process is the glass transition temperature of the resulting panel. Although this only measures a composite value for the whole sandwich of previously-cured base material and the prepreg which is cured in the press, a small increase in glass transition temperature after lamination gives a good indication that the base material has been fully cured.
Rather than describe the important topic of lay-up in further detail, we have chosen to give a substantial amount of information in Geoff Layhe’s resource booklet Multilayer bonding – what’s it all about? (PDF file, 928KB) This deals comprehensively with the topics of prepreg selection, lay-up and processing, and your understanding can be checked by answering the SAQ that follows.
Whilst we have included Sections 7 and 8 in the booklet, this is very much additional material, beyond the scope of the module. However, if you have come across signal integrity issues, and perhaps have studied our modules on that topic, you may find Section 7 of interest.
Explain to one of your colleagues how you would set about selecting the cheapest possible approach for a six-layer board, and describe the processes and procedures by which the component materials would be laid-up and pressed into a completed multilayer board.
With the tin-lead plating originally used as an etch resist, there was an obvious option of just reflowing the plating to form a fused tin-lead solder coat. Given environmental pressures to remove lead, with the consequent change to tin plating as an etch resist, this is no longer an option. We are thus left with two main strategies:
The eventual choice will depend mostly on the application, with influences from customer and fabricator. The first decision, whether to use a solder finish, a plated finish, or an OSP finish, will be dictated by the range of components used, by how many soldering processes are needed by the assembly, and by the storage life expected. The next decision point, if a plated finish is required, will be to choose between ENIG, immersion silver or immersion tin (or indeed a material such as palladium, which has found favour for component leads). Here the choice will depend more on the experiences and prejudices of the end-customer and on the materials and processes available to your fabricator. Be very aware there are many options, and always associated reliability and cost issues, so you should talk to your board supplier before making a definite decision, and seek sensible compromises.
The range of options for finishes has been explored at some length in the section on Coatings and finishes in Unit 1: now is the time to read that if you skipped past on the first skim-read!
One thing no solder resist has is the ability to remain firmly attached and unwrinkled if it is applied to a solder surface which is subsequently reflowed, so choosing a fusible finish will affect the detail of the solder mask sequence.
The unsatisfactory visual result can be circumvented by selective plating to produce an ‘SMOBC’ board (Solder Mask Over Bare Copper).
The most widely used method of producing SMOBC is to use tin as an etch resist in a conventional subtractive process, and then strip the etch resist before cleaning and applying solder mask. Solder coating is then applied just to the areas where it is needed. Figure 4 shows the process stages for solder levelling subtracted boards.
Solder mask over nickel (SMON) is a similar process, except that the flash plate used is nickel instead of tin. Nickel has a much higher melting point than tin, so does not have to be stripped off the tracks, there being no risk of it reflowing under the solder mask during either the solder levelling process or subsequent soldering.
SMON finish is, however, prone to a specific manufacturing problem. When the nickel is brushed to assist solder mask adhesion, slivers can become partially detached from the nickel plating, ‘overhang’ on each side of the tracks and other copper features that is created during the etching process, and thus cause short circuits. This is especially evident when boards are over-etched.
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Early solder mask practice was to print the final image needed by screen printing. This is still the most cost-effective process, and can even be carried out simultaneously on both sides of the board using special printers. However, most solder mask used in Europe is photoimaged, using either a ‘dry film’ type, laminated to the board in a similar way to photoresist, or a ‘wet film’ type, applied to the board and then dried. Both types then need to be photoimaged, developed and finally cured.
In order to give adequate adhesion and reliability, solder resist has to be applied to a clean surface. The aim is to remove organic and ionic contaminants, surface oxides and intermetallic compounds. The process typically starts with chemical cleaning. Finishes other than HASL then allow an intermediate stage of mechanical scrubbing. Finally, boards receive an extended wash in deionised water before being dried by baking.
Perverse as it may seem, it is reported that many board fabricators will first decide on the method of application and cure, and then on the equipment to be used, and only at the very end choose a particular material which is compatible with method and equipment! However, whilst there are many formulations, most of these are epoxy-based.
For low-cost work, solder resist patterns can be applied directly by screen printing. Printing requires little equipment, but the wiping action of the squeegee tends to remove resist ink from the leading edge of conductors and skip over narrow spaces between high-density conductors. Ink also tends to build up on the screen around the holes in the board. In order to overcome these problems, screen-coaters will apply two or maybe three layers of resist, and either move the screen between layers or clean or scrape it. Printing liquid solder mask is not a high productivity process!
Also, for high density boards, such resists are inadequate owing to ‘bleeding’ onto pads, to poor coverage between closely packed pads or conductors, and to poor registration accuracy. SM designs in particular tend to have fine surface detail, with narrow spaces between tracks and pads, and the change to surface mount encouraged a move away from direct screen printing. The 1996 IPC survey showed that most solder mask used was photoimaged, except for single-sided consumer products, where screened solder mask was used for reasons of cost.
The majority of resists used for fine line work are, therefore, photopolymers, in either dry film or liquid form, using a photographic exposure and developing process to define the required pattern in the solder mask. There are two approaches, based on the form in which the mask is supplied.
The earliest photoimageable solder masks were ‘dry film’ types, which can in theory be rolled over the board surface in the same way as photoresist is applied. But photoresist is applied to a very flat surface: the difficulty with dry film solder mask lies in ensuring that the film is in intimate contact at all points with densely packed tracks, without leaving gaps filled with air which would expand and cause delamination during wave-soldering or solder levelling.
Vacuum laminating gives a better result, but needs different equipment. The resist is held slightly away from the board while a vacuum is created in the machine. Atmospheric pressure is then allowed to force the film into contact with the board. This process can be carried out on one side, or on both sides simultaneously.
A resist film supplied at 75-100µm thickness will meet the common specification requirement for a minimum of 25µm coverage over the top of conductor traces.
Liquid photopolymer resists were developed first as etch resists for multilayer production, remaining on the board after etching, and reacting with the epoxy resin of the prepreg during lamination, saving several process steps. However, suitable formulations can also be used as solder masks, where they are described as LIPSM (occasionally LIPSR), an abbreviation for Liquid Photoimageable Solder Mask (Resist).
The earliest of these, Probimer 52, introduced by Ciba-Geigy in 1978, originally found favour (despite its high capital cost) primarily in markets which required its excellent corrosion resistance. It was not until surface mount demanded better definition that this process became more popular.
Wet film solder masks can be applied by:
In the first of these options, material is screen printed over the whole board, a process that can be carried out simultaneously on both sides of the board with special equipment. However, it is much more common to apply liquid photo masks by ‘curtain coating’, the original Probimer process, which is shown schematically in Figure 3.
Curtain coating demands close control of viscosity and conveyor speed, but will give single layers about 25 µm thick over large board or copper areas, with thicknesses as low as 10 µm achievable over fine tracks. The process allows small diameter holes to be coated without the risk of blocking them with ink.
Practical machines are more complex than indicated, because they also need a means of collecting the material that falls round the side of the board and in the gaps between boards, filtering this to remove foreign bodies which might otherwise lodge in the coating head and cause an uneven curtain, and recirculating the material.
After coating, the solvent in the layer of resist needs to be dried under controlled conditions ready for imaging. Only one side can be coated at a time, so the board also has to be dried before coating the second side. As with printing on two sides separately, this means that there will always be slight differences between the two sides in the cure state of the solder mask.
Where both sides are coated in a single continuous process, integrating two curtain coaters and two drying ovens creates a long and expensive machine! However, all types and shapes of substrate can be coated without the need for special tooling.
An third group of processes involves spraying the resist. As with any spraying procedure, all the techniques involve safety issues and the use of enclosures and extraction.
Those who would like to learn more about applying LPISM, and did not read the paper during their study of Unit 2, are recommended to read Shaun Tibbals paper Application methods and their influence on solder mask processing.
After the photopolymer has become tack-dry, it is exposed to ultraviolet light through a negative artwork, polymerising the exposed areas, so that they become insoluble in the developer. Exposure times are typically of the order of 20–90 seconds, depending on the material and exposure unit used.
Most of the original liquid solder masks were developed in 1,1,1-trichloroethane, but the use of that solvent is now discouraged because of environmental concerns. Current Ciba-Geigy Probimer materials use a mixture of nonchlorinated biodegradable solvents; most of the remainder use aqueous-based developers (typically sodium carbonate solution).
Having applied the solder mask, it needs to be cured. This can be carried out by heat or ultraviolet light or a combination of the two, depending on the chemistry of the resist. Curing removes any remaining volatiles and completes the polymer cross-linking process, making the coating sufficiently tough to withstand its application.
Curing processes that are not sufficiently controlled, especially under-curing, are the Number 1 cause of solder resist failure. What is Number 2? Adhesion failure, due to inadequate cleaning before mask application!
Note that, once solder mask has been cured, it is very difficult to shift without seriously damaging the board. Prudent fabricators inspect solder resist patterns very carefully before the board is baked. Assemblers will tell you of the times where fiducials are incorrectly read by machines, because they have been partially covered by solder mask, and of problems where stray materials which should have been washed away during development are draped over nearby land areas!
Explain to your assembly process engineer the materials and process options available for applying solder mask to a board with fine-pitch parts.
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So far in this module we have just looked at through vias, and contented ourselves with a mention of blind and buried types primarily as a preparation for Unit 11 . However, one important aspect that we need to consider at this point is what to do when you have a through via, but want the connectivity without there being a physical hole through your board.
The original reason for doing this was to seal the via to make electrical testing possible without loss of vacuum on the fixture – through holes may fill with solder during assembly, but this cannot be guaranteed, especially with small vias. There are a range of other reasons for wanting this sort of protection – David Vaughan’s article in the July 2002 issue of PC Fab identified the following:
The original way of protecting a via was ‘tenting’, using dry film solder mask, but there are actually three types of protected via:
Tenting is a reliable process, but needs thick dry film solder mask, which is bad news for fine pitch assembly. Dry film mask is also comparatively expensive. As a result, “most people have junked their dry film solder mask laminators” and the current preferred process is LPISM, with the vias plugged by a separate printing operation.
The most common plugging technique is to fill the holes from one side with solder mask material, using a conventional single-sided screen or stencil printing operation. Printing from both sides is not advised, as this will entrap voids in the hole barrel. Typically fabricators use low squeegee speeds, in order to allow the vias time to fill.
Most of the boards designed with fine pitch surface mount devices use liquid resists, as the assembly industry generally prefers the ‘gasket seal’ between stencil and pads which can be achieved by liquid resists: in contrast, dry films typically create ‘wells’. However, dry film resists are still often favoured for ‘tenting’.
Tenting is the term used for deliberately putting a mask coating over the top of a via hole. The requirement to tent (or even fill) via holes comes from the fact that closely-spaced holes can trap flux during soldering, leading to bridging.
Unfortunately, not only are dry film resists expensive, but they also do not flow enough to fill the valleys between closely-spaced conductors. DuPont’s VALU system aims to meet this problem by combining a thin coat of liquid mask with a dry film laminated on top.
Tenting can also be accomplished with liquid mask systems, but needs a separate filling stage, where epoxy inks are screened onto the board either before or after the liquid mask is applied.
Your latest surface mount design has many vias, and your test engineer is concerned that it might be difficult to ensure that the board is adequately held down by the vacuum fixture. Discuss the benefits and problems of the different options that are available.
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We talked earlier about printing as a process originally used for applying etch resist to make simple single-sided boards, and still used in certain cases for screening solder mask. The process is also common found for applying legend (also called ‘nomenclature’ or ‘screen print’). As with etch resist and solder mask, legend is nothing like a text or graphics application, because we need to apply significant quantities of material, typically in the range 50–150µm. The standard technique used for applying legend is conventional screen printing, using either UV curing or thermal curing ink. The pattern required is created in the screen, which is able to have a fine mesh, because the inks used have very small particles (in contrast to solder paste!). However, even with a fine screen, it can be difficult to obtain high definition, and care has to be taken during printing in order to prevent smudging and the transfer of unwanted material from the underside of the screen.
An alternative to this method, which produces far better results in terms of both feature definition and placement, is to use screen printing to apply an overall coat of photoimageable legend ink. Compared with pattern printing, this process wastes more ink. Also the time to process is increased because of the additional process stages of drying, imaging, developing and curing, although the final cure can be combined with curing the solder mask. However, the photoimaging process gives better results, and is often used for smaller batches where the manufacture of custom stencils cannot be justified.
Most print equipment applies legend just to one side of a board. The ink is then cured, the board inverted, and the process repeated. It is, however, possible to print on both sides simultaneously, using the same specially-designed equipment as for solder mask, but the implication of having wet ink on both sides is that extreme care has to be taken in transferring the board into a suitable curing station. Note that most of the materials used for legend are high in volatile content, and precautions have to be taken to extract the solvents.
An alternative to both processes is to use ink jet technology to apply legend directly. This is described in Mike Seal’s booklet on Direct legend printing.
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There are a number of wave-soldered designs when one needs to prevent solder pickup on parts of the board. For example:
This requirement is commonly met by specifying temporary solder masks, which mask off areas of tracking and pads from the solder wave, although physical barriers or custom pallets are often used, and there is an increasing number of selective soldering solutions.
There are three approaches to providing a temporary solder mask:
All these materials are designed to withstand immersion in solder without major deterioration, so that they can be removed afterwards. Peelable solder masks are normally printed, as this is an efficient way of applying material selectively but in one pass at a number of different places on the board, without contaminating other areas, and providing a coat of consistent thickness. Of course, such peelable masks need to be thick enough to peel easily, so coarse print meshes and the resulting poor definition are the order of the day.
Note that board fabricators sometimes use peelable solder masks as part of their internal processing. Examples are: in Hot Air Solder Levelling, to keep solder away from areas such as gold contacts; in selective plating applications, such as protecting gold electroplated areas during electroless gold plating.
Peelable masks should peel off easily from the surface and the holes, but there is often a problem in achieving complete removal: a dotted line of residual mask may be seen around the perimeter of the peeled area; material may be left in via holes.
The nature of such adhesive residue is critical: it must either not be detrimental to circuit function, or else be dissolved completely in a cleaning process. Inspectors are rightly suspicious of residues in plated holes: even if non-conductive, they may trap flux and contamination during subsequent assembly. The greatest problems are seen with liquid masks, as these penetrate the holes and vias to give a mechanical key.
Unfortunately, some resins can become very difficult to remove once they have been subjected to reflow temperatures, so it is important to make sure that the mask material has been designed to cope with the double soldering process. Improved results have also been reported from buying boards with the peelable mask a little under-polymerised, so that it reached the right physical properties only after assembly.
An alternative is for the assembly house to apply a selective mask post-reflow/pre-wave. This can be done by hand, or in volume by using selective coating equipment (dispensing or spray).
Peelable masks vary widely in their ionic properties and flux absorption characteristics, but should always be removed either before or during the cleaning operation. Not only may the mask itself degrade, but flux tends to become trapped underneath. Whether the resulting contamination originates from the mask or the flux, corrosion during life may be the outcome.
“A point I would like to make is that people don’t pay much attention to materials that are not part of the final assembly. Why worry about the latex mask? I’m just going to throw it away anyway. Well, they can have detrimental effects. The same thing applies to other ‘temporary’ materials like water soluble solder mask, water soluble temporary spacers, and water soluble tapes. Just keep in mind that every material has an effect, and every material has to go somewhere.”
Doug Pauls on TechNet, 23 August 2000
You are designing a wave-soldered product that contains a small number of non-wets. What are the assembly process options for keeping the through-holes clear? Identify and discuss any options for which you will need to involve your fabricator.
The processes we have considered above are not the only ones used during board manufacture. One example of an additional printing process is the use of carbon or silver-loaded inks to create switch pad areas, as was illustrated in Unit 1.
Another example, once very common, but increasingly non-preferred on account of its cost, is the selective plating of gold contact areas intended for direct insertion into a female connector. Whilst this is simpler than using a two-part connector, there are practical issues of tolerancing and material choice. Not only must the insertion area be of the correct dimensions to fit correctly within the socket, but the board must be of the right thickness – too thin, and the contact pressure will be insufficient; over-size, and the board will become a force fit in the connector housing.
From the fabrication point of view, wiping contacts intended for more than occasional insertion need to be made of much thicker gold than standard ENIG. A typical specification might be for 1–3µm of gold on top of 3–5µm of nickel. And the gold needs to be electroplated in order to have sufficient thickness and appropriate characteristics. Electroplating requires making electrical connection to each of the contacts (usually carried out using a shorting bar on a part of the panel that will be removed later in the process), and screening the rest of the circuit. This is one application for peelable resist, the alternative of partial immersion of the board to a predetermined level being difficult to control.
Finally in this section on other processes we must not forget the possibilities of using positive-working resists. These make it possible to remove materials selectively, so that plating can be built up either in steps or using different materials – each time further areas of the photoresist are exposed, it becomes soluble and can be developed, exposing a fresh surface for plating.
Of course, we also have the option of creating complex structures by additive processes, and these are becoming increasingly common to create high definition areas on the surface of conventional structures. This topic will be covered more fully in Unit 11.
Having completed this part of the unit, look at one of the process routes in PCB fabrication sequences, and check that you can identify the key features of each of the main processes.
Compare your answer with the relevant section above
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In this final section of our board fabrication unit, we are concentrating on ways in which the fabricator seeks to prevent defective product reaching you, the customer, and then looking briefly at ways in which the quality and reliability of a product may not be as good as expected.
What are the types of defect that you might expect to find on a board, i.e what things might go wrong with materials or process to create a faulty product?
Use your workaday experience of boards, as well as your study of the module so far, to generate as complete a list as possible. As with any lists we ask you to produce, try and create some kind of structure by grouping together similar kinds of fault.
Review your answer as you continue to read this page.
The list that we have created will probably be different from yours, not least in its arrangement. However, if you feel that you have identified a type of defect that we haven’t listed, please do drop an email to your tutor. Note, however, that we have distinguished between a defect, which is something which can be measured or observed, and the fault cause which lies behind the defect, such as the quality of plating.
Our list divides broadly into three categories:
Considering each of these in turn, the most obvious immediate defects affect DC interconnection, and affect both tracks and vias:
By now, you should be able to identify at least some of the likely causes for each of these. There are also defects that affect high frequency performance, such as incorrect track impedance, dielectric thickness, and spread in dielectric constant.
Note that these types of faults are not equally easy to spot – whilst an open-circuit may be easily distinguished from a short-circuit, high-frequency characteristics need special equipment, and the measurement of leakage is highly dependent both on conditions and on how many potential paths there are for unwanted current.
Defects that can potentially cause faults often have the same causes, but at lower severity. Two examples:
Other examples include:
Whether or not these potential faults develop into permanent catastrophic faults will depend on the application.
Finally, we have created a short list of defects that might not be apparent to the fabricator, but that will have at least some effect on the subsequent assembly process. These include:
Which of these defects might, if undetected, have implications for the reliability of the board itself and the assembly for which it is the base?
What procedures should we use in combination to screen against these defects?
Review your answer as you continue to read this page.
The term ‘in combination’ used in the preceding activity is deliberate, as no single screening method will be effective:
So we have to use a combination of screening methods, a conclusion that we shall explore further in Unit 7. Typically we inspect inner layers prior to lamination, inspect the final board, test the finished board for the intended connectivity and isolation, and carry out sample testing and process control to assure compliance with the other desired parameters.
Inspection falls into two areas, determining that the board is correct, both mechanically and visually. Mechanical inspection will normally be restricted to overall dimensions and check that routing and scoring have been carried out. The visual inspection is more searching, as this has to cover a range of possible defect types, and solder mask, peelable solder mask and legend prints may combine to obscure the underlying track.
Typically an inspector will take a view of the whole board, looking for overall problems with surface finish on conductors, solder mask and legend, and for gross misalignment of legend, solder mask, drilling and routing. These are all processes capable of having global offsets to the intended location. Visual inspection is also very good at picking up differences in colour, texture and surface finish which may indicate undesirable process changes or the presence of contamination.
The standard that is generally used for bare board acceptability is the set of criteria given in IPC-A-600. If you have access to a copy, this will illustrate for you many of the possible defects.
Given the nature of the surface, the use of automated optical inspection (AOI) for external visual inspection is far less common than is its use for checking inner layers before lamination. Not only is it cost-effective to check the inner layer before it disappears from view, but the flat surface offers good contrast between copper and laminate, and the thin copper normally specified creates patterns that will normally be very close in dimensions to those intended. As a result, quite unsophisticated algorithms can be used to compare the pattern achieved against that intended.
The correctness of interconnection pattern itself is assessed by a ‘bare board’ test. This term can mean only a partial test confirming the tracks on each outer surface without a check on inner layers and through-board connections, However, for boards containing many vias, a test which exercises the complete PCB structure is strongly recommended because of high cost penalty of assembling a faulty board. The valid point has been made that electrical test is now becoming much more important to meet the demands of greater product reliability and higher performance.
The earliest through-hole boards were tested with hard wired continuity testers, whose expensive tooling could only be justified for high-volume applications. The first machines using ‘universal fixturing’ were introduced in the early 1980s. Their ‘universal grid’ is populated with test points, originally placed on grids at 0.100 inch centres. Even that comparatively coarse grid will have 100 points per square inch, and a large grid may contain tens of thousands of points, although the number of test points actually used is just the number of nodes in the boards to be tested.
Connection between the board under test and the tester is made using rigid but flexible test pins as indicated schematically in Figure 7. An array of plates converts the fixed grid on the test bed to the positions on the board, so that it is no longer necessary to have test points on the same pitch centres as the tester.
These ‘bed-of-nails’ fixtures are very commonly found, and revolutionised board testing – in 1980, 10% of US boards were electrically tested; by 1988, over 75% were tested.
The increase in the use of multilayer boards with double-sided surface mount has dictated that both sides of the board be tested at one time. Typically, double-sided testers use a ‘clam shell’ construction, where two sets of probes are closed together around the board under test. The most flexible configuration uses universal fixtures both top and bottom, but simpler equipment may have a universal bed-of-nails underneath and a set of customised probes for the top surface.
The trend in board dimensions is inexorably downwards, and boards frequently require close test point spacing. Whilst this can sometimes be accommodated by fixture design, typically the solution has been to use testers with finer grids. When even this approach runs out of steam, the alternatives are to make special fixtures, at considerable expense, or move to a flying-probe tester.
Flying probe testers use probes that are moved across the circuit and test point-to-point8 in order to verify continuity and isolation. There are many approaches to the problems of arranging probes and board, particularly given the need to approach the board from both sides. You may like to carry out a web search for "flying probe test", as this will show many of the alternative approaches. Look particularly at the different ways in which manufacturers seek to increase the probing rate, and hence reduce the time taken. As you might imagine, it is the extended time to test that is the key disadvantage of these testers. For accurate probing, and the ability to test on fine pitches, down to 100 µm, these testers are substantially more capable than the bed-of-nails type.
8 Note that, in one respect, the flying probe is fundamentally different from the universal grid tester in that probes are not able to contact all networks simultaneously, so cannot measure the total leakage from a given network to the remainder of the board in a single measurement. Instead they are limited to measuring the insulation resistance between specific network pairs.
Because the flying probe system is very flexible, it should always be considered for board layouts that are subject to change or made only in small numbers. However, once manufacture reaches more than prototype quantities, some hard tooling will be necessary.
But is probing necessary at all? Although probing equipment has improved substantially, reliable on-target probing has been made more difficult by smaller dimensions and tighter tolerances, and merely probing the board can create unacceptable levels of damage – any probing operation will leave at least some evidence.
For this reason, a number of approaches for contact-less testing have been explored, using electron beams or non-ionising electromagnetic radiation, or capacitative or inductive methods. Cirlog, for example, scan across the entire surface of the board under test, and obtain a ‘signature’ of its displacement current. Faults are detected by comparing against data from known good boards.
The original continuity testers were driven by data netlists entered line by line, but early advances were to use a known good board first to set up the fixture, and later to act as a ‘golden board’ from which the tester could ‘learn’ the actual board pattern, and compare other boards in the lot with the sample board.
With increasing sophistication of both boards and CAD, board testing has reverted to being driven by the netlist data. Files are generated from the netlist, either to manufacture a fixture or to drive a flying-probe tester. The fixture data generation starts by sorting the X and Y locations to create the ‘personality plate’, the top plate in the fixture that matches the image of the board to be tested. The test points are then assigned to specific grid locations, representing the electronic interface of the test system. Once all test pins have been assigned to specific test grid locations, the drill files are created for the test plates. Most of these plates use a combination of G10 laminate and transparent polycarbonate plastic.
The most critical element in board test is aligning the board precisely to the fixture, and this becomes more and more important as feature size and pitch decrease. The designer should make available at least three non plated holes that can be used for test alignment.
Whilst the presence/absence of an intended track or its resistance are easy to detect automatically, many boards used for high frequency applications have tracks which are designed to have a particular impedance. This is normally confirmed by the use of time domain reflectrometry.
This test determines the reflection signature of the transmission line (two tracks measured with respect to each other, or one track measured with respect to the power/ground planes). Early TDR equipment measured dedicated test patterns, normally placed outside the working circuit. This meant undue reliance placed on the quality of design and consistency of manufacture. However, newer equipment permits testing of actual tracks on boards, and the trend is towards this direct approach.
IPC-9252 “defines different levels of appropriate testing and assists in the selection of the test analyzer, test parameters, test data and fixturing required to perform electrical test(s) on unpopulated boards and inner layers”, and is a good starting point for developing a test specification. Benke, in his article A Tutorial on Test Equipment and Methods which appeared in PC Fab in March 2002, recommended five best practices:
So far we have concentrated on aspects of board quality that can be seen, but some reliability-related aspects of board quality aren’t immediately apparent. For example, ensuring that clearances are sufficient. For this particular example, we have several approaches:
Whilst within the fabrication environment the use of X-ray equipment is generally limited to yield protection by ensuring inner circuit alignment during lay-up, the verification of isolation is well-established. Known as ‘high-potential’ (‘Hi-pot’) testing, this uses high voltages (typically 500V and more) applied between insulated tracks or planes for a given period. Not only will this indicate that the distance between isolated features is sufficient, thus screening out spacing violations and layer-to-layer misregistration, but hi-pot testing will also identify laminate voids and metallic contamination.
The ultimate ‘hidden feature’ is plating quality, although this is only one example of quality and reliability issues that relate to process control during fabrication. In order to demonstrate effective process control, test coupons are built into the board design, usually on spare material on the panel but outside the circuit area. These coupons can be removed from the board, and provide both something to test, destructively if necessary, and something to keep – proof if needed that the product met an acceptable quality standard, or at least a means of ‘backtracking’ to the quality of a particular batch.
What is built into a test coupon varies enormously between suppliers and products, but typically the test coupon will have layer markers to indicate that all the copper layers are present with the correct alignment, and other features that enable the fabricator to test the electrical and mechanical characteristics of a standard pattern. For example, there may be standard tracks for foil adhesion testing, and ‘daisy chains’ of plated through-holes, that can be used to estimate the average resistance of through connects, and subsequently temperature cycled to demonstrate reliability. A quick test, and one which is very common, is to section part of the coupon, so that the through-hole plating can be examined in detail.
Within the chemical processing environment of the fabricator, quality is much more than inspection, and the laboratory plays an important role in both process control and verification of quality. Included in their task are controls on the plating chemistry, involving both chemical analysis and plating tests.
The laboratory will also have facilities for carrying out mechanical tests, such as the peel strength of foil, some means of sectioning, to take photographs of structure and assess the thickness of plating, and equipment to carry out solderability testing, both on the materials as deposited and after artificial ageing.
In preparation for an audit visit to your supplier, explain to your Quality Manager some of the ways in which how quality and reliability should be built into the boards that your company is purchasing.
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So far we have been looking at how boards are screened for defects; our focus now changes to three significant quality and reliability issues. They are not the only such issues, but have been selected because they represent significant hazards.
Many of the failures in the printed circuit board are related to corrosion, delamination, electromigration and other effects of moisture which have been touched on in earlier units. There are, however, some other causes for failure during application, as distinct from those problems that are manifest during fabrication and assembly. Chief among these is the result of differences in temperature coefficient between the materials of which the board is made; copper has a CTE of around 15 ppm/°C, whereas most resins have substantially higher values.
The most obvious result of CTE differences is board warping. As we will see later, this can give problems during manufacture, and result in stresses on components if the board is straightened during box build. However, warping is generally a problem that is evident either on receipt of the board or after soldering (especially reflow soldering). Although having long-term reliability implications if stresses are induced because of warping, a warped board is in itself not necessarily unreliable.
However, potential unreliability due to differences in CTE is much more severe when we look at individual holes rather than the complete board. PCBs are exposed to thermal stresses, the most important sources of which are:
You will recall from Unit 1 that a fundamental property of most laminating resins is the reversible change of state which takes place at the glass transition temperature, above which the TCE of the resin climbs sharply. However, whilst the resin itself will expand equally in all directions, the constraint on expansion in the plane of the woven matrix cloth imposed by the reinforcement means that above Tg the laminate made from the resin will have a much higher TCE in the thickness (Z) direction than in the plane of the board.
Since the copper plating of the hole ‘barrel’ has a much lower TCE, aggressive thermal cycles can result in large strains in the Z direction and, consequently, on the through-holes. The plating resists this expansion, but the barrel is stressed and may crack, causing electrical failure. As indicated in Figure 8, there are a number of ways in which the through-hole metallising can fail. These are conceptually very similar to those experienced with a tubular rivet, and there are many similarities, except of course in the scale! Plated through-holes are thus the PCB features most vulnerable to damage from thermal cycling and the most frequent cause of printed circuit board failures in service.
Illustrated in photographs are typical examples of corner cracking and inner layer cracks. Notice particularly that corner cracking starts from the stress point in the inside, rather than the outside, and can be relatively harmless in appearance. However, given that cracks tend to propagate, intermittencies and open-circuits can be created in a number of places within the through-hole structure.
Failure may occur in a single cycle or may take place by the initiation and growth of a fatigue crack. For high-aspect-ratio through-holes subjected to repeated thermal shocks from room temperature to solder reflow temperatures (220–250°C) during board fabrication and assembly, failures after as few as 10 thermal cycles have been reported. The number of cycles to failure is related to the ductility of the copper plating and, with current plating technology, stress-related failures are only a problem for thick (>3.2mm) boards such as those used for back-planes. ‘Press-fit’ connectors have been used successfully to eliminate most of these problems.
Another effect that is the result of non-elastic behaviour in the materials is referred to as ‘ratcheting’. When the through-hole is heated, the epoxy expands faster than the copper, setting up a tensile stress in the copper and a compressive stress in the epoxy. In the cooling cycle, the reverse happens, with the epoxy shrinking faster than the copper, generating tensile stress in the epoxy and compressive stress in copper. If the performance of the materials were truly elastic, then there would be no problem. However, after repeated cycling, the epoxy grows, with the result that the board is thicker than in its original condition. This results in what is referred to as the ‘rotation’ of the copper land observed at the outer boundary of the through-hole, as shown in Figure 9.
Because the stress exceeds the yield strength of copper, given sufficient temperature cycling, the cumulative strain will cause a crack in the copper barrel. Thermal ratcheting is also seen in solder joints subjected to cyclical stresses
There are many ways in which process defects can impact on the reliability of a through-hole connection. Most of these are summarised in Table 5.
|Characteristic||Process affected||Defect||Impact on reliability|
|adhesion between foil and laminate||PTH drilling||copper delamination||poor barrel plating entrapment of plating chemicals|
|lamination cure||multi-layer drilling||epoxy smear; rough hole walls||poor bond between barrel and inner plane|
|smear removal||barrel copper plating||copper plating voids||solder joint voids hole fill|
|seeding for barrel plating||barrel copper plating||copper-laminate void||barrel copper crack poor bond between barrel and inner plane|
|dull drills wrong speed/feed ratio||PTH drilling||epoxy smear||non-uniform copper unfilled holes|
|copper plating||low tensile strength brittle copper||barrel copper fatigue PTH cracking|
A high-reliability piece of airborne equipment uses a 2.5mm thick 8-layer FR-4 board as a back-plane, to interconnect a number of subsidiary circuits.
Explain, using a diagram, why your quality manager is concerned when he learns that the equipment will be in an unpressurized part of the aircraft, and subjected daily to wide temperature excursions.
Surface flatness is important for the assembler for many reasons:
Whilst excessive flexibility (‘bendy boards’) gives trouble on some designs, most flatness problems come from bow (‘warp’) and twist. It is important therefore to specify the maximum pre-assembly distortion (bow/twist) allowable both for panel and individual boards. A typical requirement for surface mount boards is 0.4% of the largest dimension, which is more stringent than for through-hole assembly (0.7%).
The forces which generate warp and twist are mostly produced by differences in CTE within the board, although component layout and density may contribute. In general, the tendency for a particular board to warp will depend on the mass of the copper planes and their balance about the theoretical centre line of the structure. This will be affected by how well the board fabricator is able to balance or equalise foil spacings in the laminate structure, as well as by the uniformity of metal distribution in the design.
Typical design strategies to minimise warp and twist include:
The requirement for flatness also has an effect on the specification for even coating of the solder mask, and has frequently resulted in the omission of component identification marking (‘screen print’), as even this thin layer may lead to open-circuit joints.
Board distortion is worst when the base laminate is heated above its glass transition temperature, which occurs during both lamination and reflow soldering. Stresses that have been ‘locked into the laminate’ are relieved while the resin is soft, allowing the supporting medium to relax. Stress that may result in non-flatness can be caused by unbalanced construction or any kind of non-uniformity in impregnation, laminating pressure or temperature. Even if apparently flat when supplied, stresses present may be sufficient to produce warping when the temperature rises above the Tg of the resin, as will happen during reflow.
Warp related to lamination or subsequent baking may be possible to cure by ‘flat baking’ under applied weight. However, twist induced by lack of symmetry in design or build, or by excessive cooling rates during lamination, may lead to a board with ‘memory’, whose twist (or warp) will start returning when simply left unrestrained for a day.
‘It is possible to cool a board in a laminating press, yielding an acceptably flat product, only to have it curl up like a potato chip when it goes through reflow or wave solder’
Kelly M Schriver
Most board manufacturers are conscious of the need to supply flat products, but are constrained by the design. If you can measure and define the average shape of the physical distortion which occurs during assembly, the designer and fabricator will probably be able to reduce the problem for the next build.
Although these processes don’t appear on many simplified flow charts, one has to remember that board processes involve extended immersion in various ‘nasty fluids’. In order to prevent subsequent problems, extended cleaning is always undertaken, generally followed by sufficient baking to remove the bulk of the moisture content. Getting the board clean and dry is particularly important for reflow soldering, as the vaporisation of trapped water during the soldering process may cause delamination.
Bare board packaging has to protect both against ionic contamination and the ingress of moisture:
In order to preserve board condition and solderability, suppliers should pack the clean, dry boards in vapour barrier bags and heat seal the closures. It is important to remove excess air at the time of closure, and a nitrogen purge can be beneficial. Boards can be packed individually or in multiples, as best fits the application.
Some recommendations from users are that:
For a 4-layer board, describe as many as possible of the controls which are used to maintain quality and consistency of product.
Based on our experience, the major factors that affect interconnect reliability are, in hierarchical order:
Level 1: Copper plating thickness/quality: uniformity; ductility; elongation; tensile strength
Level 2: Material: Tg; TCE; board thickness; hole diameter; number of layers; glass to resin ratio
Level 3: Surface finish; through-hole metallisation; foil thickness; construction; grid size
Level 4: Design: pads vs. no pads on inner layers; annular ring; pad clearance
Two additional major factors not normally included in studies to determine interconnect performance are:
Bill Birch on the IPC TechNet Forum, 23 Feb 1999
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