Design for Product Build

Unit 10: Alternative approaches

In our studies so far we have covered most of the materials and processes used for the majority of electronic products. But this is not the end of the story, however tempting it may be to confine our attention to main-stream applications. After all, we should bear in mind that surface mount assembly was once itself a new idea, and only one of a number of competing technologies! So in this Unit and the next we shall be looking at some alternatives, and at ongoing trends in key areas: Unit 11 has its focus on trends and general principles; this Unit and the linked documents describe the processes and materials themselves.

Inevitably at this stage in your study of the module, you will be concentrating more on the final assignment than on reading new material. However, you will probably need some of this information for the last section in Assignment 3. We would also encourage you to become familiar with the process variants and technology trends in order to be prepared for the likely developments that you will encounter as your career progresses.

Unit contents

Why something different?

In this Unit, we are looking at alternative approaches for the materials and processes used in electronic manufacture. However, the question must first be asked: “Why use something different?” After all, mainstream processes are adequate for most applications, and one should use a different process only if there is some merit in doing so: employing a technology simply because it exists is rarely good practice!


Reflect on when/why it might be appropriate to use different processes and materials, and draw up your own list, before looking at our comments.



The way in which we have approached this Unit is somewhat different from others, in that several times we encourage you to think about the issues before reading further. In consequence, much of the key material has been formatted as answers to questions, and is found in the linked solutions rather than the main text.


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NPI and prototyping


A major application area for alternative approaches is in the manufacture of prototypes, to reduce the time to manufacture and/or the tooling cost. But why manufacture prototypes at all? Isn’t it possible just to simulate the performance aspects, and ask Marketing to visualise the product from drawings and a mock-up? Think about this before reading our response.


At the prototype stage we have a key decision to make, whether to use production equipment, so that the prototype is fully representative of final production, or to use some alternative route that cuts time and cost, but where the prototype may differ in some apparently minor but important way from the production product.


Whenever alternative materials and processes are chosen for prototypes, take care to identify every point of difference, and assess whether there is any possibility that this might impact on the performance of the product.


When using a parallel route, one certain difference is that the prototyping exercise will yield no feedback on the manufacturability of the product made by the eventual production process. After all, one of the reasons for making prototypes is to ease the transition to volume manufacture.

So the only way in which alternative approaches can be effective for prototyping purposes is if they save time or money, which effectively means either cutting out features in the process that are expensive or time-consuming, or replacing them by an alternative.


Before looking at our comments, think carefully about board fabrication, board assembly and box build, and suggest tasks where using appropriate prototyping processes may be of advantage. As part of this activity, you may wish to engage in appropriate web research.

For example, you could use search terms such as "Rapid PCB prototyping" and "PCB prototyping" + equipment, to try and establish:

Note that our answer is linked to resources which do not appear on the module map.


Supplementary information

Prototyping does not only need alternative processes, but it requires a different management approach. Although not strictly part of this module syllabus, you may wish to consult our paper Some New Product Introduction tools for a reminder of some useful techniques.


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Alternative materials and processes

We saw in Unit 1 that the materials used in making electronic products could be broadly split into three groupings, polymers, metals and glasses/ceramics. But you may have noticed that we have since confined our attention to relatively few of the available materials. However, if we look more widely, we will find many more materials used, depending on the requirements of the design.


Review the electronic assemblies with which you are familiar, and carry out appropriate web research to pull together lists of materials that might be used in four applications:

Compare your list with our answers, but bear in mind that we do not claim to be comprehensive!


Now that we have reviewed some of the alternative materials used around the board, it is time to look at the interconnect itself, where we have restricted ourselves so far to laminates consisting of a filled polymer and copper foil. Although such boards cover a wide range of constructions, the range of possible interconnect and packaging technologies is vast. If an approach is conceivable, someone, somewhere has probably tried it! Technologies can be classified in terms of:

The discussion that follows is split into two sections, on substrates and on alternative interconnect. We have deliberately kept the description short, providing additional information as links.


On first reading we recommend that you classify these technologies in the seven terms listed above. When you have read through to the end of the section and drawn your own table, compare it with our table. Where our table contains comments or qualifications, make sure that you can understand the reason for these.



As you read any resources on interconnect, bear in mind that:


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The list below includes the main properties that influence the choice of substrate material for a package or other interconnection structure:

dielectric constant behaviour at high temperatures
dielectric strength mechanical strength
insulation resistance surface finish
loss factor dimensional accuracy and tolerance
thermal conductivity flatness
thermal coefficient of expansion cost
compatibility with the interconnect layers
compatibility with the intended processing

Inevitably, real materials will not combine all the desired characteristics, and it will be necessary to prioritise the requirements, or divide up the problem, or else devise a solution using several materials. Separating out high-frequency from low-frequency elements, and high-power functions from more sensitive circuit areas, and typical ways in which this may be done. Note that decisions on technology usually have to be made very near the start of a project, and have a major influence both on the design and on the costs, and that using multiple materials is generally very expensive.


‘Unfortunately, a material that combines high thermal conductivity, high electrical resistivity, low dielectric constant, and ease of processing does not exist. Ultimately, the electrical design engineer must settle on a compromise.’

Licari, Materials for Interconnect Substrates


Specialised polymers

Whilst we should never forget that the vast majority of electronic products use reinforced phenolic or epoxy boards, many more specialised polymers have been developed, as we showed in our paper Alternative board materials. If you have not already reviewed this as part of your study of Unit 1, we recommend that you read it now.

You will find that there are many options for the resin matrix, and the choice affects both ease of use and the thermal performance of the resulting laminate. The reinforcement can also be modified, and this has a significant effect on both mechanical characteristics and the CTE. When choosing a laminate, the aim must be to get acceptable levels of glass transition temperature, mechanical strength, and CTE, all at an acceptable cost.

Specialised polymers are primarily employed for microwave applications, where a number of speciality polymers and composites have been used, most of which have a low and consistent value of dielectric constant. In an attempt to optimise characteristics, and create a structure with homogeneous dielectric properties, polymer materials can sometimes become quite complex in terms of their reinforcements and fillers.

For example, if you look at, you will find that the Rogers materials adopt a number of strategies to achieve low dielectric constant, low dielectric loss and minimum anisotropy. These include the use of microfibres for reinforcement and combining woven fibre with ceramic fillers. Appropriate choices allow the materials both to meet electronic design requirements and to match the CTE to other parts of the assembly. As a result, some microwave laminates can be used in hybrid constructions with FR-4.

Specialised polymers are also used for high-temperature applications and where flexibility is required. The latter issue is quite complex, and a whole topic in itself. However, it is interesting that polyimide materials have a role to play for both applications – with conventional glass-fibre reinforcement, polyimide is a frequent material of choice for military high-temperature boards, whilst the unsupported resin film (frequently generically referred to as Kapton®, although that is a DuPont product) is sufficiently flexible to be a common basis for flexible circuits.

Unfortunately, many electrically desirable polymers introduce their own manufacturing problems – Teflon is a well-known example of a plastic which has poor dimensional stability and is very difficult to stick to, and the processing of polyimide is also problematic.

Ceramic substrates

When there is a straight choice between a ceramic substrate and a reinforced laminate such as FR-4, ceramics are generally not selected for four reasons:

However, ceramics have the advantage of higher thermal conductivity and can be almost non-permeable, factors that make them highly suitable for semiconductor packaging. Glasses and ceramics have also been used as an interconnection medium since the 1960s, with conductive patterns either vacuum deposited (‘thin film’) or, more frequently, formed by printing a paste of precious metals (typically palladium-silver or platinum-gold) and glass frit, and firing this at high temperature to give good adhesion to the substrate. This latter ‘thick film’ technology can provide some degree of multi-layering using dielectric pastes, and also incorporate stable resistors — this is the same technology used to make chip resistors.

We have already seen in Ceramics and glasses that ceramics are strong, if brittle, and have a favourable combination of good thermal conductivity, good electrical insulation, and CTEs that are broadly compatible with silicon. In consequence, ceramics are often used in power semiconductor components, though this is not always apparent from the outside. Unless that is the component has a label warning of the presence of beryllia , a material that is innocuous in bulk, but whose powder is harmful, so that correct handling and disposal becomes essential.

The main ceramic used for thick film modules and chip resistors is “96% alumina”. That is, it contains 96% of pure alumina particles, with the balance made up of glasses and glass-formers that combine together during firing to create a dense, homogenous, impermeable substrate.

The material as-fired is slightly rough to the touch, and has a typical surface finish of 1µm CLA as measured by profilometer. Where a smoother finish is required, as for thin film applications, the surface may be glazed or lapped and polished or, more commonly, 99.5% alumina is specified – this has the same purity of alumina grain, but the structure is finer and needs a smaller percentage of glass to cement the structure.

Where enhanced thermal conductivity is required, beryllia remains a possibility, but its place has been taken by aluminium nitride. The point is made in our thermal module (at Constructional materials: ceramics) that aluminium nitride is not a single compound, and as such may have very variable characteristics.

Alumina is white, and transmits light, which may present a problem for semiconductor packaging. Alternatives are to coat the surface, to provide a package or local enclosure for the substrate, or to use a lower-purity (typically 90% alumina) material that is naturally dark brown in colour.

Co-fired multi-layer ceramic

In the same way that board designs soon “run out of steam” when only two layers of conductor are available, ceramic-based interconnection systems have struggled to create multi-layer structures. Whilst these can be made by printing multiple conductors separated by dielectric, the non-planar result typically limits the number of interconnect layers to around three, unless serious attempts are made to “planarise” the top surface, as is done with on-chip metallization.

An alternative approach was developed from the experience of making ceramic hermetic packages, for which “green” (that is, unfired) ceramic parts are assembled into a multi-layer structure, and then pressed and sintered to form a monolithic body. The materials are different, but the process is conceptually similar to that used to produce chip capacitors. By printing an interconnection pattern on some of the layers, quite a complex structure can be created.

The materials used for multi-layer ceramic packages are high-firing (typically 1450°C) ceramics, and the normal internal metallisation is molybdenum-manganese. Both ceramic and conductor are fired at one pass: hence the term ‘co-fired’. Provided that the firing conditions are correct, ‘moly-manganese’ creates very strong bonds, and the products are reliable. However, the overall process is not very flexible, the moly-manganese needs to be plated in order to be bondable, and the tooling and manufacturing costs are high.

One of several alternative approaches that is gaining favour is Low-Temperature Co-fired Ceramic (LTCC). Here the ceramic fires at the same low temperature (850–950°C) used by thick film pastes (see Thick film technology). Unfired tapes are punched to create holes, patterned with conductive pastes, stacked, pressed and sintered. LTCC has the ability to incorporate passive components, including inductors (interconnected ¾-turns on adjacent layers) as well as thick film resistors and monolithic capacitors.

Supplementary information

For more information on Low-Temperature Co-fired Ceramic materials and processes, visit the IMAPS and DuPont Electronic Technologies web sites. The latter’s Green Tape™ process is described at


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Most interconnect is metallic, although carbon films were used in some of the earliest PCB experiments. But the metal may be presented as wire, or foil, or broken down into particles and applied as a paste and sintered, or held together with a polymer matrix. As you read around this subject, think about the interconnect in the context of the completed assembly. Topics to consider are:

The sub-sections that follow describe just a few of the many options:


Discrete-wire printed circuit boards give the same function as multi-layer boards but do not involve an imaging process to form signal conductors. Instead, circuit connections are formed directly on the board using small gauge insulated wire, as shown in Figure 1. Each wire is terminated with a drilled hole, which is metallised as a via.

Figure 1: ‘Multi-wire’ construction

‘Multi-wire’ construction

The process uses as a substrate a double-sided board, which generally carries the power tracks. Adhesive is applied, then wire is then laid on the substrate using a computer controlled stylus to build up the remainder of the circuit connections one at a time.

The technique was patented by the Photocircuit Corporation, though other companies (notably Hitachi) have improved it under license: Wire-wrap® and Multiwire® are the best known trade names for this technology. Because wire crossing is allowed, a single layer of wiring can match multiple conductor layers in graphically produced boards, and give very high wiring density. However, the discrete wiring process is sequential and the productivity is not high enough for mass production. Despite this weakness, discrete-wiring boards are in use for some very high-density packaging applications.

Economic factors generally favour the multi-wire approach where manufacturing quantities are small. It may be that some of the specific test equipment in the factory is produced using this technique. The time to manufacture such a board is also much less than that of conventional multi-layer boards. The complex pre-manufacture design process need not be gone through. Modern techniques such as laser writing on sensitive laminates mean that this advantage is also reducing, the current market share is unlikely to increase.

Flexible and flex-rigid boards

In Flexible Printed Wiring (FPW), the rigid FR-4 base laminate is replaced by a flexible polymer, which can be either thermosetting or thermoplastic. FPW can be twisted and mounted in any direction, within reason, except where components are mounted directly onto it. FPW can be single-, double- or potentially multi-layer, although simple constructions are generally favoured (and rigidity increases with number of layers). Initially designed for the military and aerospace, FPW now forms about 10% of the market for PCBs.

The wide range of base film materials used includes polyesters (such as Mylar®), polyimides, fluorocarbons and aramid paper (made from nylon fibres). Factors, other than cost, which influence the choice are strength, flexibility, dimensional stability, dielectric constant, and moisture absorption. The most commonly found base is polyimide (the best-known of which is Du Pont’s Kapton®), which has excellent stability, tear resistance and high-temperature performance, and generally appears as a thin brown transparent or translucent sheet.

FPW usually has separate adhesive layers to bond together the layers of the board, and the hard-to-bond nature of many of the flexible polymers means that careful preparation of the surface is often required, during both manufacture of the foil-coated primary laminate and any multi-layer laminating. Thermosetting, thermoplastic, and modified thermoplastic organic polymers are all used as adhesives for flexible circuits, depending on the application. [Modified thermoplastics combine a structure similar to a thermosetting adhesive with the flexibility of a thermoplastic]

Other differences between FPW and rigid board practice are:

Figure 2: Make-up of flexible printed wiring

Make-up of flexible printed wiring

A flex-rigid board is one which combines rigid areas, in which components can be mounted, with integral flexible portions which serve either to join two or more rigid portions or to link a rigid area to components that cannot be mounted on the rigid portion of the board such as ‘hot running’ components mounted on external heat sinks. This direct board-to-board connection technology removes the need for a back-plane where space is critical, and increases interconnection reliability for high risk applications.


For more details on the techniques used and the design, fabrication and process issues, read our paper Flexible and flex-rigid circuits. Flexible circuitry is a common component in high-density structures, and has found many applications in Chip-Scale Packages.


Making smaller vias

Whatever the type of high pin count device, one limiting factor is the ability of the board to provide all the interconnections needed within the space available. This is true both of the main assembly board and any module interposers incorporated in MCMs or BGAs. The market-driven trend to higher interconnection density is forcing the use of an increased number of layers, and new board technologies capable of finer tracks and smaller vias, to keep pace with component packaging technology.

The standard design rules for PCBs are seemingly endlessly being driven down to smaller and smaller dimensions. It is now common to see 150µm tracks and gaps in PCB designs, with the sizes of via holes and pads reduced from 0.75mm pads/0.5mm vias to 0.5mm/0.3mm. For conventional (subtractive) board technology, what the limits are depends on:

As regards track and gap, 100µm/100µm is about the current limit for volume manufacture, with 150µm vias.

Chandler of GEC-Marconi makes the point that smaller vias and pads are the key factor in increasing density; Schmidt of Dyconex states that 80% of any layer is determined by the holes and pads, but only 20% by the tracks and gaps. Pressure for higher density has therefore resulted in a focus on vias:

Competing technologies able to make vias of 75µm diameter or less are laser ablation (used amongst others by GEC-Marconi in their MicroTrace®) and plasma etching (used by licensees of the Dyconex DYCOstrate™). The methods have different economics (one shot per hole, as against one etch per batch of panels), different methods of pattern control (direct CNC, compared with photo-imaging), and different hole profiles (parallel or slightly tapered, rather than the ‘pit’ of isotropic etching).

Given that BGA and flip-chip packages have constraints on ball spacing, another consequence of the pressure has been to create tracking dense enough to allow more traces between each bond pad. This has stimulated the development of alternative techniques to produce smaller tracks/gaps. These generally involve ‘plating up’ within areas defined by photo-resist, as this approach gives better definition than etching, particularly when the thickness of the copper is similar to the gap width. Such techniques have already made 50µm/50µm parts available, and these dimensions can be reduced to perhaps 30µm/30µm.

Whilst most assemblies continue to be made of epoxy-glass (FR4-type) laminates, there are many alternatives. Particular emphasis has been on reducing both the dielectric constant and losses at microwave frequencies, for which materials incorporating PTFE (Teflon™) are commonly used, reinforced with woven and/or micro-fibre glass. Recent work has done much to overcome the high Z-axis expansion and adhesion problems associated with the basic polymer.

Figure 3 illustrates something of what can be achieved by non-drilling high-density technologies. However, although these give increased tracking capability to the designer, and enable more functionality to be packed into the space available, ultimately it is the surface area taken up by the components that determines the minimum size of a system board.

Figure 3: Views of high-density PCBs, which emphasize the role of pads and holes in determining overall interconnection density

Views of high-density PCBs, which emphasize the role of pads and holes in determining overall interconnection density

Source: Dyconex

“Pushing the envelope”

When high tracking densities are needed, the etching process has limitations, in the same way that conventional drilling limits achievable via sizes, although the process boundaries are continually being extended downwards for both. Read our paper High-Density Interconnect for an insight into the different techniques that are employed.


‘Hybrid’ technology

Hybrid circuits are so-called because their manufacture combines many different materials and techniques. The technology developed because of three drives:

The first silicon integrated circuits were developed in the early 1960s, but these had modest functionality and required many support components. With other technology limitations in both passive components and the interconnecting board, one target was to find a technology which would integrate all the circuit elements.

Two main approaches were used to deposit both components and interconnections onto an sheet of electrically-insulating material:

Thin film’, where extremely thin (in the range 20nm–1µm) conductive, resistive and insulating films are formed by vacuum deposition, and patterned by etching or laser machining. Two main technologies competed:

nichrome tantalum
conductors gold on a chromium ‘seed’ layer
to enhance adhesion
resistors nickel-chromium tantalum nitride
capacitor dielectric silicon dioxide tantalum pentoxide
capacitor electrodes aluminium tantalum

Both sets of materials can produce dense interconnect patterns, but have limitations on the range of resistors and capacitors available, and are not well suited to building multi-layer structures. Also, the glass substrate, most often chosen because of its smooth surface, is not very robust.

Thick film’ (more correctly ‘printed-and-fired’) technology, uses conductive, resistive and insulating pastes containing glass frit, deposited in patterns defined by screen printing and fused at high temperature. The patterns are coarser than for thin film, but the films are much thicker, typically in the range 5–20µm, the range of resistors is wider, there are more possibilities for building multi-layer structures and the (typically ceramic) substrate is stronger and better able to withstand subsequent assembly. Figure 4 shows schematically some of the components of an assembled thick film circuit.

Figure 4: Thick film materials used for making conductors, resistors, capacitors, mounting pads, and crossovers

Thick film materials used for making conductors, resistors, capacitors, mounting pads, and crossovers

Polymer thick film is an alternative process (‘printed-and-cured’) which is conceptually similar, but replaces the glass frit with a loaded polymer. The materials have advanced considerably since their first introduction, but there are concerns over their long-term stability.]

For both technologies, the original aim was a totally integrated film circuit. For example, a great deal of effort was expended on active devices, and thin film transistors were built using evaporated films of semiconductor compounds. Although these had reasonable electrical characteristics, attempts failed in the end to match the performance of silicon, and even the technically much simpler thin film capacitor has been all but abandoned.

The reasons for this failure are inherent in the concept of integration itself, because an integrated assembly generally precludes the possibility of rework, which might otherwise increase overall yield by identifying and replacing faulty components. This increases very considerably the requirements on individual component yield, as the first-pass yield can otherwise be extremely low.

As a result the all-film integrated circuit gave way to the ‘hybrid’ which:

The growth of hybrid technologies in the 1970s led to the development of:

1 If the manufacturing yield of a component is y (0<y<1), then the yield of an assembly containing N components will be N^y. A circuit integrating as few as 50 components (not a very complex assembly), each with a yield of 95% (quite high), would have a predicted overall yield of only 7.7%, although this calculation makes the simplifying assumption that all components being assembled have the same individual yield.

Unfortunately, the printed-and-fired conductors used by thick film technology have limited current-carrying capability and high resistance compared with bulk copper. One way of combining the heat-sinking properties of alumina with bulk copper is to use ‘Direct Bonded Copper’; DBC is produced by enabling the reaction between copper and alumina that takes place just below the melting point of copper, creating a permanent bond. The copper-clad alumina is then etched to create a pattern. DBC is very useful for making assemblies of power semiconductors.

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Alternative semiconductor processes

As well as having choices to make at the interconnect level, we also have alternative processes for semiconductor attachment – it is not an invariable rule that all semiconductor dice need the protection of a package so that they can be soldered to the interconnect substrate!

Direct chip attach

The ultimate act in reducing the size and affect of the package is to remove it altogether. This is not a new idea and was developed during the 1960s for thick film hybrid circuit technology. Early attempts were not very satisfactory: chips were difficult to characterise before mounting and prone to damage during assembly, so that overall circuit yields were low. The main problem with COB remains that of producing ‘Known Good Die’ (KGD), avoiding the cost and difficulty of rework by testing each device before it is placed onto the board. Work continues to focus on ways of testing the silicon chips without fixing them into a package, so that they are known to be fully functional under all operating conditions.

The COB process itself has the same three steps as in package assembly:

The die bond to the circuit board substrate must withstand the usual thermal, mechanical and environmental conditions expected of a standard packaged component. This is usually achieved by adhesive bonding, which has the advantage of providing a thermal and mechanical cushion between the significantly different CTEs of the silicon material of the chip and the epoxy resin of a PCB substrate.

The die pads then have to be connected to the wiring on the board in order to complete the circuit - before this is done the die is isolated, like a package without any legs. Of the techniques used, gold wire bonding is most common, but TAB is attractive for thin packages.

Finally, the die and its bonds have to be protected from mechanical damage and chemical or moisture attack. This is usually achieved by local encapsulation of the die. An epoxy polymer material is dispensed through a syringe system over the bare die and cured to form the protective barrier. This method is commonly called ‘glob topping’. ‘Glob top’ materials are specialist polymers designed to provide: the necessary flow characteristics during dispensing; a mechanically tough surface once cured; long life resistance to environmental conditions.

The area to be glob topped can be defined to a limited extent by controlling the travel of the dispensing system. However, it is more usual to restrict the fluid flow mechanically, either using solder mask or other material cured in advance, or by creating a ‘dam’ of non-slumping polymer, which is dispensed as a first process stage during glob-topping (Figure 5).

Figure 5: The dam-and-fill process for glob-topping

The dam-and-fill process for glob-topping

Alternatively, a lid can be bonded onto the substrate to cover the die, but such lids are usually filled with glob-top resin for protection against vibration, chemical attack and moisture ingress.


The reliability of a joint depends on the stress applied to it. In the case of two materials of different CTE, joined together by pillars of solder, the stress in the solder will be a function of:

This last is particularly important – you may recall that IBM’s purpose in developing the column BGA was to reduce the stress caused by mismatch between the ceramic body of the part and a laminate substrate.

So how do we deal with components with small balls, where both connected area and stand-off have been reduced? The answer lies in applying an adhesive between the surfaces, which spread the stresses caused by differential expansion, and reduces the stress applied to individual solder balls. This process is referred to as ‘under-filling’, and is generally carried out after the devices have been tested electrically, in order to make the rework task possible.

A range of resins are available for this purpose: all need to be very pure, and exhibit good adhesion, with compatible CTE. Another desirable property is that they should not be too rigid, so that they can comply with the joints as they expand and contract.

Whether or not under-filling is needed by any particular application will depend primarily on the physical characteristics of components and board and on the expected environment of the end-product. If the requirement involves continued temperature excursions during life, then under-filling is recommended. Under-filling is also advantageous if it is anticipated that assembly will be subjected to mechanical stresses during life, as these have a comparable effect to the strains imposed by thermal mismatch. Mobile phones are an example of such a product.

But how do we get the adhesive between components and board, given the small spacing? A few of the materials used are applied before solder assembly, and combine the functions of flux and underfill. However, this method often produces voids in the interface, which can make local stresses worse. Probably the preferred option is to apply the resin after soldering, making use of the fact that capillary attraction will draw fluids into the gap. This requires adhesives of suitable viscosity, containing small filler particles. Unfortunately, resins with suitable CTE and thermal conductivity require substantial amounts of filler, and much development work has been needed to produce underfills where the filler particles are not trapped at the edges, leaving the material at the centre of the chip relatively unfilled and with a higher CTE.

Video 1: Underfilling operation on transparent test flip-chip, showing capillary action


Given the right material, and considerable advances have been made over recent years, a package can be underfilled in under 5 seconds. Material is ‘piped’ along one edge (or two adjacent edges), and allowed to be pulled underneath the package before subsequent applications are made. Depending on how far one is prepared to allow the resin extend beyond the package boundary, three or four applications of resin may be needed, with a final ‘piping’ of resin around the periphery to create a proper fillet.

Self Assessment Questions

Explain to your Production Manager why s/he might need to invest in a machine for underfilling µBGA packages.

Show solution


Power devices

When it comes to bonding to the face of the die, aluminium and gold wire bonds create most bonds, but these are generally fine wires (<33µm diameter), so are limited in their current-carrying capacity. For power devices, the die bond both supplies current to the device and takes heat away from it, but we need high-current face connections, which requires leads of substantial cross-sectional area to be used.

Ultrasonic wire bonding of large diameter aluminium wire (up to 1.2mm) can be carried out using annealed wire (for comparative softness) and a specially constructed bonder (Figure 6). A requirement is to dissipate the necessary energy in the bond, rather than destroy the die or the bearings in the bonder, and careful consideration has to be paid to supporting the assembly rigidly and designing the package and jigs sufficiently robustly.

Figure 6: Ultrasonic wedge-wedge bonding of large diameter aluminium wire
1 - bonding tool; 2 - transducer; 3 - wire clamps;
4 - aluminium wire; 5 - wire feed capillary; 6 - wire shifter

Ultrasonic wedge-wedge bonding of large diameter aluminium wire

The alternative, which is most used with high-current devices, is to solder tapes or ‘bridges’ to the die surface. This process needs a special die metallisation which is both solderable and solder resistant.

The advantage of a solder approach is that top-surface soldering can be combined with die bonding. A typical production machine incorporates solder dispense, die placement, solder dispense on top of die, a bridge cut and plate system and an in-line solder reflow furnace with programmable temperature profile and inert gas atmosphere.

Other alternative techniques

The history of semiconductor assembly contains many by-ways, and a number of totally different approaches to the assembly problem, most of which still have at least some adherents for specialist applications. We have linked a number of these to resource notes:

Hermetic encapsulation is used for specialist purposes, both for high-reliability applications and in the manufacture of modules.

Whilst most wafers are sawn, Alternatives for die separation are available.

See Die bond materials for information on the many alternatives to silver-loaded epoxies.

For an approach to chip face bonding that is potentially easy to automate, and has been used for applications such as Smart Cards, see Tape Automated Bonding.

For direct chip attach, but with the chip mounted directly face-down onto the substrate, see Beam leads for a method that was tried and generally found wanting, and Flip-chip for any even older method that still offers advantages, and is used in many types of Chip-Scale Package. There is a very useful resource on flip-chip at

As you browse through these materials, look particularly for changes that have happened in recent years, and for evidence of current interest and use. Bear in mind that some of these papers started life several years ago, and one always needs to refresh one’s knowledge base . . . this is a deliberate challenge to start browsing, by way of preparation for Unit 11!

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The first polymer packages were ‘conservatively designed’, in the belief that a relatively large mass of plastic and a long interface path between lead-frame and polymer were needed to impede the transmission of water vapour and thus delay the onset of failure. Improvements in the purity of materials and the passivation of the die surface have transformed this situation, and the moulding now primarily serves a mechanical function.

A result of this change is that many of the package formats standardised in the 1970s are now unnecessarily inefficient in their use of space. For example, the SO- series of integrated circuit packages is thicker than it needs to be, has too wide a lead spacing, and can accommodate only relatively small dice. In response to this the SO concept has been extended to include a wide range of package outlines which are often grouped under the heading of TSSOP, or Thin Shrink Small Outline Package.

The trend continues: Khadpe reports that the focus in Japan is on ‘keihakutansho’, or light, thin, short and small packages, with some parts now being less than 1mm thick. With conventional lead-frame construction, this places constraints on the thickness of materials (die, lead-frame and moulding) and the profile of internal wire bonds, and lays considerable emphasis on the management of the internal stresses.

The Ball Grid Array (BGA)

The most immediate solution for increasing the number of available leads on any package is to reduce both the lead width and inter-lead spacing. The progression historically moved from 0.1" (the dual-in-line package standard pitch), through 0.05" (the SOP standard) and some short-lived intermediates, to 0.025", adopted for the first of what were termed ‘fine pitch’ Quad Flat Packages.

Encouraged by improvements in solder paste, printing and component placement, which maintained solder joint quality despite reducing pitch, the trend continued, with packages of increasing lead-count being designed progressively with 0.5mm, 0.4mm and 0.3mm pitch (or the inch equivalents). However, it was soon apparent that defect rates increased markedly with the finer pitches, with both open-circuits and bridges resulting from problems with paste volume control and misalignment of both print and package with the board. In consequence, a number of assemblers who trialled components with the finest pitches have reverted to more conservative designs, and 0.4mm (0.016") is the smallest pitch in common use.

However, one way of ‘getting more people round the table’ had already been proven at 0.1" pitch - for some years, microprocessors had been packaged in ceramic-based Pin Grid Arrays, typically with three concentric squares of pins on a 0.1" grid. Whilst in this type of pre-made package all the pins normally lie outside the periphery of the chip, other designs of ‘interposer’ between silicon and board can be devised where the whole of the area is taken up by pins or their equivalent. The pin count advantages of using the entire package under-surface area to provide interconnect points, rather than just the edge of the component, can be seen in Figure 7. Making use of more of the area under the package allows the designer either to incorporate many more connections or to space them further apart.

Figure 7: Graph demonstrating the advantages in number of pins per package of an array as against a perimeter approach

Graph demonstrating the advantages in number of pins per package of an array as against a perimeter approach

The advantages of the area array had also been demonstrated by IBM using solder balls between chip and board for direct chip attachment. Whilst this resulted directly in the flip-chip technology discussed in Section 8, its concept also provided an alternative to PGA pins, and gave rise to the Ball Grid Array (BGA).

BGA elements

There are four basic elements which combine to make a BGA, as shown in Figure 8:

The basic elements can each be implemented by a range of techniques, and therefore the number of feasible variants of BGA package is enormous. BGA is a generic concept rather than a specific product, with ‘101 variants likely to follow the early mainstream types’. The sections which follow outline the main variants.

Figure 8: Basic elements of BGA technology

Basic elements of BGA technology

The reasons why BGAs have quickly become a widely used technology include:

Not that the BGA is totally without problems: Table 1 briefly lists some of the benefits and disadvantages of this packaging technology.

Table 1: Issues relating to BGA technology
perspective advantages disadvantages
Manufacturer standard interposer for any chip attach technology new generic process
  solution to high I/O chips requirements unknown reliability
  testable for KGD requirements  
Assembler ‘standard’ SMT process inspection
  high yield cleaning
  independent of chip attach technology rework
  reworkable reliability
Designer higher I/O chips take less space uses more system board layers
  less noise and cross talk  
  higher speed performance  

Polymer BGAs

The main volume BGA product currently available is the OMPAC developed by Motorola, whose construction is shown in Figure 7. The main technologies involved in this version are:

As with conventional lead-frame assembly, the trend is towards manufacturing devices in an array which is subsequently diced (much like the wafer) to separate the individual units.

The PBGA grouping of BGA types refers to the two main characteristics of PCB substrate and polymer encapsulation. There are therefore a large number of technologies and techniques which can be involved even in a PBGA package. These include wire bonding TAB and flip-chip for die attach/interconnect, and transfer moulding and ‘glob top’ for encapsulation.

Figure 7: Schematic cross-section of an OMPAC package

Schematic cross-section of an OMPAC packag

Ceramic BGAs

The ceramic versions (CBGA) of the package again have a range of variants. The most common of these is the standard ‘column’ BGA product offered by IBM (Figure 8). The main technology features are:

No lid is required in this case as the die is face down and the underfill protects the chip and circuitry from environmental attack.

Figure 8: Schematic cross-section of a Column-BGA

Schematic cross-section of a Column-BGA

There are a number of process alternatives for the CBGA format, which include:

Figure 9: Schematic cross-section of a thermally-enhanced CBGA package


Whilst the polymer BGA was developed with several different pitches (1.5mm, 1.27mm and 1.0mm), the middle of these (0.05") has proven the most common. Arrays are often completely populated with balls, but sometimes mirror PGA practice by using only the outer ranks of leads. The arrangement will depend on the number of connections, the die size and the design rules for the PCB interposer.

In the quest for ever-increasing density, many manufacturers have introduced devices whose connections are on a finer pitch: 0.03" is an emerging standard. Conceptually, the only difference between these ‘Micro-BGAs’ and a flip-chip is that the µBGA has an interposer – the challenges associated with alignment and inspection, and the need for underfill, are otherwise very similar.

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The Chip Scale Package

The trend towards packages which are very little larger than the dice they encapsulate has given rise to the acronyms SLICC (Slightly Larger than IC Carrier) and the more frequent CSP (Chip Scale Package). This is an area where there is much activity, and some ‘blurring of the edges’ in definitions, but the term ‘chip-scale’ is generally restricted to devices where the ratio of package area to die area is less than 1.2:1.

Figure 10: The Fujitsu SON package for memory products

The Fujitsu SON package for memory products

Two assembly variants using conventional lead-frames are shown in Figure 10, which illustrates how the Fujitsu SON package was derived from the TSSOP, and is now only a fraction larger than the silicon chip itself.

Clearly this approach can only be applied where the IC lead-outs can be moved to the centre of the silicon, as with memory devices. Such devices have another advantage, in that many of the connections (power and data) between packages in the system need to be connected in parallel. This has made possible the building of three-dimensional arrays for those requiring the ultimate in packing density. Yields can be maximised by testing (and even burning-in) each layer as a separate entity before final assembly.

For more general application, the lead connections need to appear at the periphery of the silicon. In the package shown schematically in Figure 11, a form of TAB interconnect is used to connect the chip pads to a polyimide circuit whose tracks lead to the ball bump sites, which are copper/nickel/gold pads with 90/10 tin/lead solder bumps. An elastomer bonds the mini-substrate to the chip, providing the necessary cushioning for the chip once it is attached to a system substrate. Finally the assembly is fixed into a protective lid by an epoxy fill, which also covers and protects the chip connectors. Also seen in Figure 10 is a section of an assembly with two CSPs mounted back-to-back on a board – here the packages have a similar construction to the schematic, except that the back of the die is exposed, a configuration which helps remove heat.

Figure 11: Schematic cross-section of one style of SLICC package (above)
Cross-section of two SLICC packages mounted on opposite sides of a PCB (below)

Schematic cross-section of one style of SLICC package (above); Cross-section of two SLICC packages mounted on opposite sides of a PCB (below)

The SLICC package, designed for optimum board space usage, is only a fraction larger than the silicon chip itself. Pad pitches range from those that provide little more challenge than the standard BGA pitches to pitch dimensions which are comparable to die pads. Thus the placement for a SLICC package will depend on the actual pitch used on the device. If it is of the order of 1.00 mm then standard equipment and a BGA approach should be capable, but at 0.20 mm a flip-chip approach will be required.

Supplementary information

More information on the generic styles if CSP in our resource note Chip-Scale Package.


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Multi-Chip Modules (MCMs)

History and development

Military systems need very high resistance to environmental damage and therefore tend to protect components from the environment using ceramic substrates with sealed metal lids. In a complex system, where space and weight is a major problem, these types of packages are too cumbersome. Unfortunately, mounting the bare dice for an entire complex system into a single package would make production costs extremely high due to low yields, even if there were a very low failure rate per wire bond.

MCMs were initially developed for military use as a response to this yield problem. MCM packages are easier to assemble than multiple single device packages, and can be tested at intermediate stages, which improves yield and therefore reduces the cost of the system assembly.

MCMs have also been used in the commercial market, where putting multiple memory chips into a single package is an attractive option if the package manufacturing yields achieved are high enough.

MCMs, like BGAs, are really a group of packaging technologies. Unlike BGAs, where the common themes are technological (solder pad array contact, substrate chip carrier, chip attach and interconnect, and encapsulation), the only commonality between MCMs is that there is more than one chip in the package.

What sort of MCM?

Three classifications of MCM are generally recognised, differentiated by the material and interconnect technology used for the substrate:

Figure 12: 4-chip MCM in PGA format

4-chip MCM in PGA format

A question often considered, if not always articulated, is ‘where is the dividing line between an MCM and a daughter board?’, and there is certainly a ‘grey area’ between these. One appropriate decision criterion might be the percentage of the surface area occupied by silicon, but this can be difficult to estimate, and products such as that illustrated in Figure 13 are in case highly silicon-intensive. Is this a true MCM?

Figure 14: High-density assembly using a combination of µBGA and QFP components

High-density assembly using a combination of µBGA and QFP components

An example of a border-line case which is more frequently seen is the single-in-line memory module (SIMM) used in many computers. This usually contains a number of SO-format active devices mounted on one or both sides of a small plug-in multi-layer board, and is considered in every way to be ‘just another component’.

External interconnects

MCM packages may use either through hole or surface mount external connections:

Practical MCMs

Most MCMs integrate power-dissipating devices within a relatively small volume, so thermal management of the package becomes important, although progress has been made in reducing both the operating voltage and power dissipation of semiconductors. Many different approaches have been taken, most of which seek to minimise the thermal impedance of the path from heat source to the environment by a combination of:

Figure 15 shows an MCM for a high-power application, where the interconnect has been built on a thin laminate directly bonded to a finned heat sink.

Figure 15: MCM for a high-definition TV application
125mm x 125mm; 32 ICs; 172 R/Cs
3,301 connections, 2,457 bonds; 366 I/Os
profiled aluminium heat sink

MCM for a high-definition TV application

Source: Dyconex

Like BGAs, MCMs are a group of packaging technologies, albeit with more than one chip in the package. There are a very large number of different MCM types, but these tend to use standard board connection techniques, for example, through hole pin grid array (PGA), QFP gull-wing or BGA solder ball. The placement equipment that is required is therefore no different to that required by the equivalent standard product interconnect type. However, the more complex an assembly, the more attention has to be paid to verifying correct function, and the more difficult becomes the task of making test connections to the unit. The most fruitful strategy for this appears to be to build in a degree of self-test and diagnostic capability into the system architecture.

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