Design for Product Build

Unit 11: Developments and trends

Any unit that entitles itself “Developments and trends” runs the risk that the technologies it describes will already be “old hat” before it is published, even when this is done electronically. So the important part of this Unit lies more in giving an understanding of the driving forces than in describing the areas where the technology is currently making progress.

We start by reviewing the progress of electronics manufacturing technology to date and the drivers that have affected it. Then, under four headings that start “Areas of Change”, we suggest some questions that influence developments in these sectors, and leave at least something to your exploration, as well as providing some links of our own on key topics.

Finally, we add a reminder that technology change has implications for all the members of the team, and talk about the importance of keeping up-to-date.

Unit contents

The development of interconnect

Electronic connection has developed considerably since the pre-war days of individual components wired together1. In less than 70 years we have seen the maturing of printed circuit board technology as well as the amazing development from single transistors to extremely complex integrated circuit devices, supported by significant improvements in passive components and the introduction of many new or vastly-improved materials.

1 There is much web-based material on the history of electronics. We liked Mike Harrison’s compendium at, especially his Interesting old adverts for electric stuff.


Before reading further, reflect on your knowledge of interconnection development: What changes have there been? When were the advances made?

Then try to establish which are the important drivers for the process, first by reviewing what you already know about the development of the electronics industry, and then by carrying out a web search. But don’t spendtoo much time on this activity unless you have a passion for the History of Science!

Some hints for a preliminary search:

If you find it difficult to come any conclusions from your skim reading of selected items from your search, you might like to reflect that one frequently sees the results of drivers more readily than the drivers themselves. What could you conclude from reviewing a timeline of the advances in electronics which have taken place over the past 150 years?

Beware! Just putting in the search term "timeline" will give you 100M+ entries . . . "timeline of electronics" gets just 6 different entries but only one that is relevant in any way; "history of electronics" + "timeline" gave 165 different links, some of which helped; "timeline" + "electronics" gave 1,750,000 links!

Hint: Particularly if you are short of time, you might want to take at A timeline for electronics, which we created as part of our own research, and which summarises many of the key events and advances.


The most cursory review of the subject indicates that electronic products now have a higher level of integration, with circuits that are substantially more complex and offer greater functionality – you have more computing power in your desktop than the systems which landed man on the moon2. From the timeline, you will notice that progress isn’t consistent, with bursts of activity following fundamental discoveries. You will also find that concepts often precede the application by some years, requiring advances in equipment, processes or materials in order to come to fruition. Today’s ideas become tomorrow’s prototypes and only eventually standard practice.

2 That point is well made in the Semiconductor Industry Association 2005 Annual Report, which talks about “40 years of exponential progress”. The article by Dan Hutcheson is recommended.


Historically, some of the research which drove electrical and electronic progress was purely academic, but the bulk of progress came from working on concepts and applying them to real practical problems, both to solve the problem and to make money. Edison claimed that his ideas were 1% inspiration and 99% perspiration, but the latter was certainly inspired by the fact that patents could be turned into dollars!

The progress of electronics has been accelerated by applications, particularly in conflict situations. As examples of this, look at the way that military considerations promoted first the development of radio and radar, and then of computing. Particular advances were made in the 1960s with the drive to put men on the moon, and through the 1960 to 1980s military and aerospace users drove reliability and small size, to some extent regardless of cost.

That is not to say that there were never voices saying “It will never fly, Wilbur!”. It was a senior man at IBM who felt that the world-wide demand for computers would be only in single figures, and transistors were at first considered mere toys.

Whilst historically progress was driven by the military, for the past 20 years or so market forces have changed, with consumers driving cost, quality, time to market, size, ease of use and other performance features. Why the consumers? Because consumers now have more discretionary spending power. Not being constrained by reducing budgets as are the military, they are more subject to the dictats of fashion, although electronic lifestyle products have to:


What is currently driving progress? Think about this in the light of your research so far, and write your own notes before looking at our comments.


In our review of what is currently driving progress we identified new technology, but only as one of four elements. However, that perhaps takes away from its importance, if not as a driver, at least as a enabler of progress. In particular, as regards electronic assembly, one can argue that the development of the silicon chip has actually been the main driver – ever-increasing complexity led to a requirement for more connections, this stimulated package development, and in turn these new packages forced changes both to board fabrication practice and assembly methods.

The silicon chip is not the only factor that may be described alternately as driver or enabler; others in this category are materials and manufacturing methods. And we should not lose sight of the fact that, despite continuing advances in all three areas, there continue to be occasions where silicon, materials and manufacturing methods all prove to be constraints on development, rather than enablers.

Supplementary information

If Moore’s Law and Rent’s Rule don’t mean much to you, read our paper The development of interconnect. This describes how the developments in silicon technology forced changes in component packaging and drove the transition to surface mount.


Of course, whenever progress is attempted in many directions at once, there will inevitably be lots of dead ends like the BetaMax video recording system, and a number of quite promising developments, such as Bluetooth, where the uptake of a useful technology was delayed for a long time because of an insufficiently favourable price:performance ratio.

Dead ends . . . or just before their time?

“For every invention that makes it, many don’t. This month PC Plus pays homage to fifty poor technology souls that – despite grit, determination and a very good idea – didn’t ever make it in the real world. The list was created by a panel of technology evangelists and experienced journalists who discussed hundreds of products, innovations and concepts that were never meant to be.

“Alongside badly conceived ideas and designs, many products in the list were just too far ahead of their time. Commodore’s Amiga CDTV was launched in 1991, as the world’s first set-top box computer; a decade later Microsoft and Intel are trying again to push the ‘ Media Center’ PC as a home entertainment component. Likewise, Pioneer’s Laserdisc system brought cinema quality pictures into the home on a series of double-sided 12in discs almost twenty years before DVD caught on. It failed to catch the imagination of film studios that instead focused on the burgeoning home video market.

“Other items making the list include Nokia’s first attempt at a mobile games console, the N-Gage, which has yet to make an impact on handheld gaming; and Amstrad’s em@iler phone, which Sir Alan Sugar promised would ‘take the market by storm’ at its launch in 2000. It’s still trying to this day.”

PC Plus magazine, November 2005


Technology itself has become a fashion, although some of the gloss disappeared from the sector when the bubble burst at the turn of the century. Nevertheless, technology is being driven by the growth of the internet, fuelled by increasingly cost-effective personal computers, and by the way in which technology can enhance leisure pursuits. Can you remember what you did before you (or your children) played computer games? Or how you added movement and sound to your family album before the days of camcorders? Or how you passed a long journey without the aid of your Walkman or iPod?

Whilst the moral value of some of these technology drivers may be questioned, the fact is that such pressures have driven much of recent development. Typical electronic products are characterised by short product life, by early replacement with enhanced products and by rapid price erosion for the rest. In order to service this industry, electronics professionals have to provide interconnection solutions in a much shorter time than before, and designs have both to work first time and be manufacturable in volume and in profit without major re-work. Which is why Design for Manufacture in its broadest sense has been a theme throughout the whole of this module.

Having considered the drivers of change, in our next four sections we are looking at specific areas of change as they affect :

Whilst these are not the only areas of change, and there is considerable overlap even between these four categories, they do represent the most significant areas in which progress continues to be made.


For all the “Areas of change” topics, we have written a short introduction and indicated a way of approaching the topic, rather than give a definitive answer. However, for those of you who enjoy a visual way of looking at the material, we have posted a mind-map for each of the topics that was developed by one of the team. This is available both as an HTML page with an image and as a .mmp file, for those who use MindJet software and would like to personalise the map and make their own additions and comments.


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Areas of change: board materials

In Unit 10, under the title Alternative substrate materials, we considered some alternative materials, both specialised laminates and some ceramic materials. However, we did not cover the whole range of possibilities. Part of the reason was that using the term “substrate” leads one to assume certain additional constraints. Whilst the essential requirements for a substrate are only that the material should be stable, adequately insulating and able to make permanent bonds to some kind of metallization, the implication is also that the material needs to be flat, rigid, and able to form multi-layer structures. In our opinion these are not essential requirements for every substrate in every application, even though there will usually be certain preferences, for example that the material should have a CTE that is compatible with the components to be fixed to it.


Given this more widely-embracing concept that a substrate material needs only to be stable, adequately insulating and able to make permanent bonds to some kind of metallisation, write down as long a list as you can of materials that, in the right conditions and for the right application, might form a suitable electronic substrate.

Now read our list of Potential electronic substrates.


In our answer, we indicated that the range of possible materials was much wider than it first appears. However, conventional materials have the advantage that prior experience enables us to avoid the pitfalls that may be associated with alternatives. For example, ceramic materials require different metallisation, as well as different designs.

Although a wide range of possibilities exists, our choice must always be guided by the requirements of the application. In the sections that follow we have suggested three specific areas where the requirements will be different, and our choice may be other than a conventional epoxy-glass laminate.

Dealing with heat

The drive to increase functionality, combined with miniaturisation, mean the component density, and even the functions within the components, create more heat in a smaller space. Materials are rated to certain temperatures, and when these are approached reliability and performance will be impaired. The designer is faced with either getting the heat out, or using materials that can withstand the higher temperatures, or using a combination of the two approaches.

Ignoring the heat issue is no longer an option, as Tony Kordyban indicates somewhat humorously in his “Timeline of electronics cooling history” that forms Table 1.

Table 1: Tony Kordyban’s “Timeline of electronics cooling history”
1940s vacuum tube computers thermal engineers are created to add heat sinks, fans and water cooling to keep tubes from burning out every five minutes
1960s transistors replace tubes thermal guys become TV repairmen
1970s TTL integrated circuits re-hire thermal guys
1980s CMOS replaces TTL thermal specialists re-trained to write C code
1990s high-frequency CMOS; introduction of the 100W microprocessor mechanical designers and analog circuit gurus take 3-day courses in CFD
2000 worst thermal problems ever electronics cooling viewed as a legitimate engineering discipline

A suggested research approach

If we consider both approaches as they apply to the laminate, we need to try and identify answers to the following questions:

You will already have much of the information you need here, but there are many web sources available. Or you could review the materials in AMI4817 Design for Thermal Issues.

Our thoughts are presented as a mind-map in Dealing with heat (original mind-map: right-click and save for local editing).


Supplementary information

As with all problems, we have to remember that design, materials and manufacturing are inextricably interwoven. An example of the holistic nature of electronic packaging is given very positively in the paper by Alexander Craig and Stephen Martin, Automotive Packaging Is a Powerful, Problem-solving Tool (Advanced Packaging, June 2005).


Substrates for high-frequency use

Over the past several years there has been a dramatic rise in communications, which has taken many forms: data; video; audio. The thirst for news, entertainment and general communication has given rise to a need to increase channel bandwidth, speed and availability. To achieve this we use much higher frequencies than previously, and new materials, devices and techniques have been developed to handle these increasing frequencies.

A suggested research approach

You will probably have a good understanding of the high frequency issues from your own work, from your study of modules such as AMI4814 Signal Integrity and EMC, and from the comments made earlier in this module about high frequency. However, if you were starting from scratch, the questions you might ask would be:

As indicated, searching for subjects such as “signal integrity” will give many clues here.

Our thoughts on some of the issues are summarised in Substrates for high frequency use (original mind-map: right-click and save for local editing).


Low-cost approaches

Much emphasis is put upon the ‘high tech’ end of electronics, which is seen as the ‘exciting’ bit, offering new capabilities, new opportunities, greater speed, smaller size, and more functionality. It is therefore very easy to over-specify the requirements for the product you are designing and making. In consequence, there is a drive to achieve low-cost solutions, especially for products selling into a competitive environment.

A suggested research approach

Much of the emphasis on this module has been on pushing the boundaries of the technology, or at least providing solutions for the professional market. So researching low-cost solutions may well require a “back to basics” approach, looking at a range of possibilities for cutting every last penny from the manufacturing cost. Typical questions one might ask would be:

Key web site search terms might be: low-cost, phenolic, "board punching".

Some of our thoughts are contained in the mind-map on Low cost approaches (original mind-map: right-click and save for local editing).


Bear in mind that our suggestions, though valid, may not represent all the possible approaches for cost paring. Faced with an absolute requirement to make for the lowest possible cost, an engineer will need to collect a great deal of information on the cost build-up both of the final assembly and the individual components, performing at least an informal cost benefit analysis for each, and preferably engaging in some level of Value Engineering.

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Areas of change: board processes

Not only are the materials of interconnect changing, but so are the processes by which even laminate-based boards are made. Here the requirement is to achieve higher density, and we have identified three interconnected subjects for research in this area:

All these are aimed at shrinking the dimensions of both the track and the through connections between layers, and at enabling components to co-exist with vias, rather than be forced onto separate areas of the board. The driver is the industry need for ever-higher density to deal with more complex integrated circuits, especially area arrays. The interconnect to those devices becomes more complex, and requires signals to be transferred into several layers of the board very close to the I/O itself.

In order to save space and enable very fast/short interconnect requires both a reduction in via size (‘micro-vias’) and the increased use of:

New techniques have therefore been developed for creating the holes and plating them, and for filling (‘plugging’) the vias to avoid assembly problems.

Unfortunately, the greater the density of fine tracks and micro-vias, the more expensive the substrate becomes, and only certain elements of the circuit may require this higher performance. To meet this challenge, techniques have been devised where the main board construction is a ‘standard’ multilayer, but high-density/high performance areas are created by adding layers of interconnection to the structure.

A suggested research approach

This is an area where the researcher will find a number of different approaches, but generally some preferences for specific technologies, though these preferences may vary from country to country, or at least continent to continent. Ideally one should aim to compare and contrast practice in Europe, the USA and Japan.

A structured approach to micro-vias, via filling and sequential build-up acknowledges the fact that these issues are very much inter-dependent. A typical range of questions would include:

Web searches for these key terms will yield much material that would need to be concentrated and assimilated. We have split our own thoughts on these topics into three mind-maps, though there is inevitably a degree of overlap:

Micro-vias (original mind-map: right-click and save for local editing)
Via filling and Via-In-Pad (original mind-map: right-click and save for local editing)
Sequential Build-Up (original mind-map: right-click and save for local editing)


Because increasing use is made of high-density techniques, and many students will not have the time to carry out their own research, we have written our own paper on High-Density Interconnect, which we would encourage you to consult.

Encouragingly, high density interconnect is becoming main stream, and the comments made by Motorola to Mike Buetow (Let’s Get Small, Circuits Assembly, 1 January 2006) are enlightening, suggesting that all the significant steps forward have been made, leaving room only for evolutionary improvements. Yet there is commercially considerable growth in this market area, given that many industries have not already adopted high density interconnect. Suggested reading on this is Hayao Nakahara, Microvia Market Dialing Up Big Gains (Printed Circuit Design and Manufacture, August 2004).

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Areas of change: technology approaches

We chose the term Technology approaches to cover what is a diverse set of different ways of building electronic structures, but arguably the description ‘structures’ should have been in the title, because this is the first time that we have included materials that have a definite third dimension. These structures cover a very wide range of technologies and sizes, and differ markedly in the application areas. Some are relatively generic approaches, whereas others have been developed for specific purposes; all will probably only be available from a restricted range of specialist suppliers.


Be prepared both for state-of-the-art technology to come from some very surprising sources, and also for the basic concepts to have arisen many years ago. Flip-chip started with a 1964 IBM patent; some of the attempts to build circuits on ceramic, or to use polymer materials to integrate components into boards, are almost as old. What has happened over the years is that processes and materials have improved, so that what was once a marginal process has reached maturity. So it is reliable, and well-understood, but perhaps has been sidelined from the main-stream for cost or technical reasons. When you are viewing some of these technologies, always try and understand why it is that they have not progressed beyond their niche market share.


Embedded components

Up to this point we have treated the PCB as a passive carrier of electrical signal and power between the components, and to the outside world. Strictly speaking this is not the case, and every substrate has some associated electrical characteristics, such as resistance, capacitance and inductance. Of course, circuit designers have relied for many years3 on the multilayer structure having inherent capacitance, and at high frequencies significant inherent inductance also. We use our knowledge about these when designing for high-frequency applications.

3 The concept of using closely-spaced power and ground planes as a parallel-plate capacitor for power supply decoupling was invented in the 1920s! See Joel S. Peiffer, The History of Embedded Distributed Capacitance, Printed Circuit Design and Manufacture, August 2004.


However, the values of resistance, capacitance and inductance associated with standard tracks are usually too low to be useful, and it is often important to position decoupling devices close to the signal source, or disperse them along the length of the signal path. Doing this by adding discrete resistors and capacitors has an associated cost in terms of purchase and assembly, and they occupy valuable space on the substrate. Have you ever wondered if it would be possible to replace some of those many passive components that litter complex boards? If so, you are not on your own: there are evident advantages to building such devices into the fabric of the board itself, and for many years engineers have been trying to integrate resistors and, in particular, decoupling capacitors.

Integrating resistors means changing the resistivity of parts of the conducting film on the surface or on an inner layer, perhaps using polymer thick film materials instead of copper; creating a capacitor of any significant size means increasing the dielectric constant of the board material, at least locally, by incorporating areas with high dielectric constant into the structure; making an inductor demands track designs with substantial mutual inductance.

The passive components we have considered so far are restricted in value and performance by what can be integrated into the laminate structure. However, the reason for the section title of “Embedded components” is to open up the possibility of embedding discrete components within the structure. This approach widens4 the concept whilst achieving the same end result, of creating a circuit board that is more than just passive interconnect.

4 A wider range of components is indicated in The Impact of Embedded Components by Michael Fitts (Advanced Packaging, October 2003).


A suggested research approach

For researching this topic we have suggested a structured search which considers both the design approaches involved and the practicalities of embedding components within interconnection structures. A suitable sequence would be:

A search for "embedded passive components" will yield significant and helpful results, and there is some discussion in our resource note on High-Density Interconnect.

Caution: For simplicity, you would be well advised to concentrate your researches on substrates that are basically polymeric in nature, and later review how these compare with hybrids, where passive components are generally created on the surface of ceramics.

Our thoughts are summarised in the mind-map Technology approaches: integral components (original mind-map: right-click and save for local editing).


It is noteworthy that, despite early promise, embedded components have been used less than might have been expected. This is in part due to the comparatively poor performance of embedded components compared with their discrete equivalents, but another possible reason, that no adequate design and simulation tools are available, is suggested by Mike Buetow in Let’s Get Small.

Supplementary information

The article Embedded Passives, RF Design by Loy D’Souza (Advanced Packaging, November 2004) discusses general design challenges facing mixed-technology RF designs, as well as the more specific challenges of incorporating embedded passive technology into these designs.

However attractive a technology may appear, we should of course only use it when it gives the optimum outcome. This is the view taken about the use of embedded components by Richard Snogren in When to embed: advice on factors to consider and questions to ask before layout (Printed Circuit Design and Manufacture, February 2004).


Provided that appropriate techniques and materials are used, a laminated structure is able to embed almost any component, provided that its physical format is suitable, and that it will survive board processing. Although there is little sign of significant take up of the technology, it has in the past proven possible to integrate optical components within the board, as shown in Figure 1.

Figure 1: Cross-section of board showing integrated optical waveguides

Cross-section of board showing integrated optical waveguides

Source: Siemens Diematic

Hybrids and circuits on ceramics

Building a circuit on ceramic has been practiced since the mid-1960s, and remains a construction of choice for some high-reliability markets. Circuits built on ceramic frequently use bare chip techniques and hermetic packages to create dense, reliable assemblies, but there are also applications that take advantage of the better thermal properties of ceramic compared with polymer materials.

Conductive and resistive films may be created by printing patterns of glass-containing inks, and firing these at high temperature (so-called ‘thick film’), or by a variety of other techniques, including vacuum deposition (‘thin film’). Different technologies have different feature sizes and employ different ways of creating isolation, crossovers and multilayers, or of working round these challenges.

As well as building circuits on the ceramic surface, it is possible to create multi-layer ceramic structures using either high-temperature ceramic processes, such as those used for packages and ceramic capacitors, or materials with lower firing temperatures. These so-called LTCC (“Low Temperature Co-fired Ceramic”) materials also offer opportunities for integrating passive devices as part of the structure.

Generally ceramic-based circuits are restricted in size and complexity, and it is quite common to restrict the use of the techniques to producing independent modules. These are (usually relatively small) circuits that are pre-assembled by a specialist manufacturer, then supplied to the board assembler as a component. Such devices may be chosen where:

A suggested research approach

A structured search for ceramic-based technologies would be a serious undertaking, involving collecting answers to questions such as:

Fortunately, we have already written some notes on Thick film technology, which you may already have consulted as part of your study of Unit 10.

Thoughts from a different author are presented as a mind-map on Technology approaches: Hybrids (original mind-map: right-click and save for local editing).


Supplementary information

LTCC is a useful enabling technology, particularly where volumes are significant or the requirements severe. More information and insight into this technology in the following articles:

Glenn E. Oliver, Designing with LTCC, Advanced Packaging, July 2004.

Liang Chai, Aziz Shaikh and Vern Stygar, LTCC Integration of Passives, Advanced Packaging, February 2004.

Joe Mazzochette, LTCC on Metal, Advanced Packaging, April 2003.

Marybeth Allen, Thermal Process of Low-temperature Cofired Ceramics, Advanced Packaging, December 2003.


Flexible circuits

Flexible circuits have traditionally been relatively simple structures of polyimide and copper, using rolled annealed foil in order to achieve the necessary resistance to continued flexure. You will find different specifications and constructions, depending on whether the laminate is designed for continuing regular flexure, or just occasional movement. There are limitations in the number of layers in a flexible circuit, so combination flex-rigid assemblies are a common way of combining some flexibility with complex multi-layer structures. Lamination (or rather the potential for delamination) and loss of adhesion are issues within this technology.

Sometimes the designer has limited space, or requires that the electronics should fit into a shape which cannot be satisfied using a rigid (standard) PCB, made out of rigid phenolic, epoxy-glass or ceramic. At other times, the circuit may need to be a part of an interconnect that moves, hinges, or twists. In these instances the designer may choose to use a flexible (flex-) circuit as the substrate.

For other applications, the designer may need part of the circuit to be flexible, but with other sections kept rigid, for example, because of components or mechanical connectors. This can be achieved in a number of ways, for example, by adding a stiffener to the flexible material in a local area, or using the flexi circuit as the interconnect between ‘standard’ boards. Flex material is used also in a number of component packaging applications because of its thinness.

But design is not the only reason for the use of flexible circuits. For example, with the low-cost product shown in Figure 2, the rationale for using a flexible substrate was not just to have a thinner component, but also to make it possible to manufacture the part on a continuous reel-to-reel production line.

Figure 2: Flexible substrate for a low-cost watch made by reel-to-reel processing

Flexible substrate for a low-cost watch made by reel-to-reel processing

Source: Siemens Diematic

A suggested research approach

Starting from a zero knowledge base, a suggested approach is to seek answers to the following questions:

Many of the answers will be found in the Unit 10 text and the associated paper, Flexible and flex-rigid circuits.

Another contributor’s thoughts are presented in mind-map form in Technology approaches: flexible circuits (original mind-map: right-click and save for local editing).



In our resource note on The Chip-Scale Package, which you will have encoutered during your study of Unit 10, we introduced the idea of a three-dimensional assembly within a package, either by taking individual packages with end terminations and stacking these, or by mounting die on top of each other and staggering the bonding to package pads. This type of three-dimensional approach has proven particularly attractive for the development of high density memory devices, although Buetow (op.cit.) states that Motorola have identified a need for such stacked packages to contain more than just memory.

However, we should not forget that potentially the whole assembly can be build into three dimensions. Examples of this can be found as early as the 1980s, where products such as telephone handsets were built using the plastic moulding as the substrate for interconnect and assembly. A number of different ideas were developed and patented, but most of the ideas have fallen by the wayside, despite the attraction of apparently simplifying the assembly and reducing the number of components and interconnections.

The main reason for the minimal take-up of true three-dimensional assemblies has been difficulty of manufacture from a number of causes:

The potential for a three-dimensional approach, at least for small structures, is still there, and some of the difficulties can now be overcome by combining electroless deposition processes with direct imaging. So the future may have that extra dimension . . .

Micro-Electro-Mechanical Systems (MEMS)

Most definitely three-dimensional, although on a much smaller scale, is a group of technologies generally described by the term Micro-Electro-Mechanical Systems (MEMS). Recently these have attracted media interest both as accelerometers, used to detect impact for automotive airbag applications, and as steerable micro-mirrors used to create very large displays. As you will see from Figure 3 the MEMS product is highly “photogenic”!

Figure 3: MEMS used to create an ultra-sensitive motion detector

MEMS used to create an ultra-sensitive motion detector

Source: Sandia National Labs: Image Gallery 2004

Supplementary information

You may be interested in the pictures of the range of steerable micro-mirrors made by MEMX Incorporated – you can even see them move (though turn the sound off first!).


So, what is MEMS technology? The best explanation that we can find was that by the MEMS and Nanotechnology Clearinghouse, in What is MEMS Technology?, which describes MEMS as being “the integration of mechanical elements, sensors, actuators and electronics on a common silicon substrate through microfabrication technology. Whilst the electronics portion is fabricated using standard integrated circuit process sequences, the micro-mechanical components are fabricated using compatible ‘micro-machining’ processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices.”


“MEMS technology is based on a number of tools and methodologies, which are used to form small structures with dimensions in the micrometer scale (one millionth of a meter). Significant parts of the technology has been adopted from integrated circuit (IC) technology. For instance, almost all devices are build on wafers of silicon, like ICs. The structures are realized in thin films of materials, like ICs. They are patterned using photolithographic methods, like ICs. There are however several processes that are not derived from IC technology, and as the technology continues to grow the gap with IC technology also grows.

“There are three basic building blocks in MEMS technology, which are the ability to deposit thin films of material on a substrate, to apply a patterned mask on top of the films by photolithograpic imaging, and to etch the films selectively to the mask. A MEMS process is usually a structured sequence of these operations to form actual devices.”

MEMS and Nanotechnology Clearinghouse, The Beginner’s Guide to MEMS Processing


The view given is of a technology that will revolutionise many different parts of the industry, and allow the development of new smart products. Certainly this is an enabling technology deserving of study. However, there are significant problem areas to be borne in mind when incorporating MEMS into electronic products, which centre around the problem of encapsulation – MEMS are generally sensitive both to contamination and dust, and would normally be packaged in a hermetic environment.

Supplementary information

More information on MEMs packaging issues in:

Daniel D. Evans, Advances in MEMS Packaging, Advanced Packaging, April 2004.

Ken Gilleo, MEMS Packaging Update, Advanced Packaging, September 2005.

Terrence Thompson,, MEMS, Opto and Nano-Scale Technologies: A Booming Market Poses Challenging Questions, Chip Scale Review Magazine, March 2005.

SIMTech, Wafer-Level Chip-Scale Packaging for MEMS.



MEMS have been part of the electronic scene for the past ten years, and are only now coming into volume production. A similarly ground-breaking technology, with elements in common with MEMS but on an even smaller scale, is described as “nanotechnology”. The original idea that was the essence of nanotechnology was of manipulating things at atomic level to build tiny molecular machines. For an introduction to this subject visit What is Nanotechnology? at the IEEE Virtual Museum.

Researchers in this area have created a number of interesting products, and one of these, “nanovelcro”, is suggested as a potential replacement for solder. Certainly concepts demonstrated by researchers in nanotechnology, such as carbon nano-tube hooks, will eventually find their way in mainstream electronics manufacturing.

Supplementary information

More information on selected nanotechnology ideas in:

Tom Becker, ‘Self-Healing’ Material Seen In Movies Is Real Possibility, MATR News, 16 July 2003

Young-Kyun Kwon, Applications of Nanostructured Materials, ITAMIT Workshop, 6 August 2004

Paul Deymier, ‘Growing’ Microchips from Proteins, Advanced Packaging, March 2004


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Areas of change: component packaging

So far we have concentrated on the interconnection infrastructure, with perhaps some incorporated components, and seen how changes have reflected advances made in silicon packaging. In this final “Area of change” we are looking first at the considerable progress that has been forced on other component areas in order to match advances made in silicon packaging – there is little use in having a really miniature microprocessor if all the peripheral components are comparatively enormous! Finally, we will be reviewing progress made in the packaging of integrated circuits, and looking in a slightly different way at topics introduced in Unit 10.

What all these different components have in common is a challenge for the assembly house, particularly as products get simultaneously more complex (usually with many more leads), smaller and more fragile. So, as you review the different packages and component styles available, we would urge you not to assume that ‘smaller’ always equates to ‘better’. In fact, using smaller components may add unnecessarily to the cost, without giving any performance advantages.

Always think of assembly from the perspective of an assembler . . . Also, as components shrink, think about the impact on the manufacturer of the component. Is striving for a smaller component going to lead to process changes that will impact adversely on quality? Or on yield? The task of the product design team is to select the component that will be most fit for purpose in the specific application.

Chip components

The first comment here must concern the emergence of ever-smaller chip components (Figure 4). [It is ironic that, at the same time, active devices have become larger!] Driven by the need for smaller assemblies, passive devices have over the years moved from 1206 and 0805 progressively to smaller parts, so that most circuits will now only use parts larger than 0603 for high values of capacitance, and in many applications 0402 parts are commonly selected.

Figure 4: Chip components are getting smaller!

Chip components are getting smaller!

Source: Siemens Diematic

However, the smaller 0201 and 01005 sizes are generally both more expensive to purchase and more difficult to use, although a great deal of attention has been given to this, both from the stencil and pad design aspects and from machinery designer. Some insight into that is given by Fredrik Mattsson and his colleagues in Design and Assembly of 01005 Passives Using Pb-Free Solder, Circuits Assembly, 1 May 2005.

Naturally, capacitors with the smaller dimensions have thinner dielectrics and less available area, so typically have low voltage ratings and small maximum values. The easiest way to demonstrate this to yourself is to search for different body sizes and dielectrics at one of the manufacturer’s web sites.

A suggested research approach

For an in-depth view of the progress made in chip components, we suggest the following structured piece of research:

For a start on web-based research, the device manufacturers present considerable information on their web sites. Examples are;; One difficulty you may expect is that there is often insufficient information available on comparative cost, which is a key factor influencing the uptake of the smallest parts.

Our view on the issues, given in mind-map form, is at Advanced packaging: chip components (original mind-map: right-click and save for local editing).


Back in the days when assembly houses had equipment for the automated insertion of dual-in-line packages, it was quite common to encounter resistor networks, typically with 8 or 15 resistors in a 16-pin package. Nowadays, resistor networks will be packaged in SO- equivalents, but fewer are found. Part of the reason is a change in circuit requirements, but in many ways resistor networks are less attractive than formerly, because individual components are now cheaper and easier to assemble. They may also be smaller, although some types of passive are available in an area array package, as in Figure 5.

Figure 5: ST Microelectronics integrated passive CSP

ST Microelectronics integrated passive CSP

Source: Siemens Diematic

For capacitors, multiple units can be found, but there is an inherent problem (which becomes worse as dimensions reduce) of preventing solder bridges between the lands of isolated components. This is one reason why the emphasis has rather been on integrating capacitors within the board structure, as we discussed earlier.


From the manufacturing point of view, chip resistors and capacitors have the advantage that they are very much a commodity product, with little variation other than size. The same cannot be said of connectors, where there continues to be considerable growth in the number of different types on the market. Many of these are developed in order to meet specific applications, and some designs present considerable challenges to the assembler.

A suggested research approach

You will already have encountered a range of connectors in your study of Unit 3, and its link to the Harwin paper Connecting to Printed Circuit Boards. For a wider view, we suggest the following sequence of activities:

For a start on web-based research, the device manufacturers present considerable information on their web sites. Key manufacturers and search terms include: ITT-Canon; mictor; coaxial; optical; straddle mount; DIN.

An interesting aspect to reflect on is the comparatively large number of connector types that are now presented in tape-and-reel format, intended for surface mounting and reflow soldering. At long last engineers seem to have accepted that a surface mount part is adequately attached for most applications!

As before, our mind-map of thoughts on this topic is at Advanced packaging: SMT connectors (original mind-map: right-click and save for local editing).


Not all connections are electrical connections, but we need to remember that light is also used as a data transmission medium. In many cases the connectors used will bear some physical resemblance to electrical connectors, except that the active core of each optical fibre will need careful preparation and alignment with its partner in order to reduce the losses. Where the optical fibre is embedded within a board structure, then the connection will take a different form, one solution to which is shown in Figure 6.

Figure 6: Coupling to an embedded waveguide

Coupling to an embedded waveguide

Integrated circuits

As with passive components, there has also been a trend over the past 15 years towards encapsulating integrated circuits in smaller, thinner packages. This move, progressively through fine-pitch QFP to BGA has in many cases resulted in packages whose exterior is little bigger than the die itself.

The diversity in semiconductor encapsulations is accompanied by a bewildering number of acronyms, although it can generally be said that formats can be divided into peripheral packages and area arrays, with a further sub-division of area arrays, between types that connect through a ball or bump and “landless” types, where solder paste creates joints direct to metallisation on the package. The choices here make a significant impact on both yield and ease of manufacture, although the assembly process is conceptually the same regardless of the device type.

Where space allows, majority usage is for leaded components (SO- and thinner variants), with BGAs for components with more connections. For applications that are more space-critical, area arrays with balls on smaller pitches (Figure 7) are preferred, and many of these will approach the ideal of the Chip-Scale Package..

Figure 7: Different types and sizes of µBGA/CSP

Different types and sizes of µBGA/CSP

Source: Siemens Diematic

A suggested research approach

Anyone needing an overview of the issues would have a considerable amount of work to do in identifying the different types of device and understanding the issues associated with each. A structured approach would be:

For a start on web-based research, the device manufacturers present considerable information on their web sites. Examples are;;;;

Our thoughts, distilled into mind maps, have been split into two sections, the first on the larger BGA and LGA packages, and the second on CSPs:

Advanced packaging: BGAs and LGAs (original mind-map: right-click and save for local editing).
Advanced packaging: Chip-Scale Packages (original mind-map: right-click and save for local editing).


Recommended reading

We covered the topic in Unit 10, but now is the time to read our resource note The Chip-Scale Package if you have not already done so.


Chip-scale is only part of an ongoing evolution of packaging, which is inexorably moving towards greater complexity and thinner packages, as discussed by David Tuckerman in Looking into the Future of Chip-Scale Packaging: What’s Next for This Still-Evolving Technology? (Chip Scale Review Magazine, July 2005).

Of course, all progress comes with a practical consequence – a thinner package needs a thinner wafer, and this creates real problems for the manufacturer. An ultra-thin wafer will only flex without breaking (Figure 8) if there are no surface scratches! Changes in packaging may also require the assembler to use non-standard processes, such as those considered under Alternative semiconductor processes in Unit 10.

Figure 8: Handling wafers with thicknesses in the region of only 50µm is very challenging!

Handling wafers with thicknesses in the region of only 50µm is very challenging!

Source: Siemens Diematic

Use of chip semiconductors

Another area of change that has “threatened” for over 30 years is the use of bare chip semiconductors, avoiding altogether the need to use encapsulated parts. Unfortunately, the practicalities of processing, and the yield implications for multi-chip assemblies, have militated against the wide adoption of bare chip methods. But perhaps the pressure for miniaturisation is once more making flip-chips an attractive technology – more about this by Gail Flower in What’s up with Flip Chips? (Advanced Packaging, August 2004).

Supplementary information

More about this technology in our paper on Flip-chip.


One problem area with semiconductor assembly is that devices intended for wire bonding will have peripheral connections, which are inevitably too close together to allow a large flip-chip bump. Figure 9 suggests one way in which the problem can be overcome, using additional layers of interconnect on top of the die to redistribute connections over the whole die surface. This is a technique used both in manufacturing Chip-Scale Packages and for flip-chips mounted direct onto an assembly.

Figure 9: Comparison between flip-chip and wafer-level CSP
Flip-chip: peripheral pad arrangement; min. pitch 150µm; average bump height 65µm
Wafer-level CSP: area array pad arrangement; pitch 800µm; average bump height 280µm

Comparison between flip-chip and wafer-level CSP: Flip-chip: peripheral pad arrangement; min. pitch 150µm; average bump height 65µmComparison between flip-chip and wafer-level CSP: Wafer-level CSP: area array pad arrangement; pitch 800µm; average bump height 280µm

Source: Siemens Diematic

The redistribution of die connections offered by the Wafer-Level CSP (WLCSP) approach has several benefits that are discussed by Douglas Bolen in Emerging Packaging Technologies Offer Many Design Advantages for High-Speed Connections (Chip Scale Review Magazine, July 2003). Not only does the approach improve the electrical and thermal performance, but it allows die of different designs from different manufacturers to be packaged on the same footprint.

Higher-level integration

The concept of building an entire system in a single package has been the dream of many workers over the past 30+ years, as you will find if you search for the terms "wafer-level integration" and "System-In-Package". In fact, it was the pursuit of this dream that lead to the methods of interconnecting dies within a wafer that lead to the WLCSP described in the last section. But practical systems usually require more than integrated circuits, which means that the “System-In-Package” needs to contain passives as well as integrated circuits, combining many parts with multiple interconnections within a single outline.

Creating a viable SIP combines the complex design issues described by Paul Smith in Getting your SiP to Market (Advanced Packaging, September 2003) with some practical method of integrating the components. An example of a SIP approach is the Multi-Chip Module that was briefly described at the end of Unit 10. The consensus seems to be that alternatives to single-chip integration (the so-called “System-On-Chip” (SOC) should use a “hybrid” approach, using that term in its widest possible meaning, to embrace three-dimensional chips, package stacking andmulti-chip modules, combining elements created with different technologies within a single package. More information about this in Tummala, Raj and Sundaram, Next-generation Packaging Materials (Advanced Packaging, June 2004).

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Design, material and process implications

All these areas of change have implications for the design, for the materials used, and for the processes. For example, we have already indicated the implications for placement of selecting the latest, smallest capacitors. It would not be realistic to make an exhaustive list of the issues, but we have tried in the next sections to suggest the main problem areas and give you leads to help you explore them in more detail.

Design issues

Compared with 20 years ago, CAD systems are now more than competent to deal with the smaller dimensions and increased complexity of current designs. However, the designer needs to have a better understanding of the three-dimensional nature of the product, in order to be able to avoid problems during assembly. An example of such a requirement is indicated in Figure 10.

Figure 10: 0201 to larger component spacing
200 micron or larger spacing is recommended; larger spacing may be necessary for heat sinking components such as large BGAs, QFPs, PLCCs, or connectors

0201 to larger component spacing

Source: Siemens Diematic

At the same time, the designer needs to be aware of the materials and processes used, so as to be able to choose appropriate pad designs. Here the change to lead-free solders, with their poorer wetting characteristics has compounded the problem. In consequence, there is now more divergence of opinion than formerly as to the optimum pad design.

Materials and components issues

As Motorola commented in relation to High-Density Interconnect, materials are showing evolutionary improvement, rather than anything revolutionary. We have selected two materials-related examples:

We cannot ignore the commercial pressures for improvement, especially within the semiconductor industry. Two examples here are:

Figure 11: Silicon wafer on film, showing street cuts

Silicon wafer on film, showing street cuts

Source: Speedline Technologies

So far the materials and components trends have been positive, but we should not forget the potential downside in some areas. An example is the challenge of package proliferation complained of by Harry Rozakis in Cost Implications of Package Proliferation (Advanced Packaging, September 2004).

Process issues

At least some of the trends require changes to equipment. For example:

Figure 12: Dip module for fluxes and adhesives

Dip module for fluxes and adhesives

Source: Siemens Diematic

Other upgrades may be needed in areas such as assembly vision systems, as the camera images are significantly different (Figure 14). Note also that extra requirements such as checking on the integrity of each bump/ball before placement, add significantly to the computing overhead.

Figure 14: CSP and flip-chip camera images

CSP and flip-chip camera images

Source: Siemens Diematic

Using smaller components is generally accompanied by increased problems, the tombstoning shown in Figure 15 being a typical example.

Figure 15: Tombstoning: a typical defect with 0201 technology (SEM and X-ray views)

Tombstoning: a typical defect with 0201 technology (SEM view)Tombstoning: a typical defect with 0201 technology (X-ray view)

Source: Siemens Diematic

As Achong and Chen comment in BGA Land Pattern and Assembly Issues (Printed Circuit Design and Manufacture, February 2004), shrinking BGA packages from 1.27 mm to 0.4 mm may save board real estate, but raises a host of new considerations from coplanarity to rework to reliability!

Problems of this type point up the need for generally tighter process controls. This point is made by Peter Grundy in a paper that is still recommended reading: The impact of high technology on best practice electronics manufacturing.

The potential for defects in any process, let alone one that uses the latest technology, can give rise to reliability issues. Combined with an increasing tendency on the part of consumers to pursue claims through the courts, the need is greater than ever for putting in place management control systems that will mitigate the consequences of disaster. This is a topic covered by David Huntley in his paper Mapping and Traceability Minimize Recall Costs (Advanced Packaging, June 2003).

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Keeping up-to-date

Whilst there is little need to stress the point to AMI students, who are actively engaged in Continuing Professional Development, experience with lead-free conversion suggests that a higher proportion of companies need to be proactive in managing change, and have in place programmes that will keep them updated with the latest technology. It is no longer sufficient merely to react to customer requirements.

Ideally this updating should be carried out in co-operation with your suppliers. SO, if you get the opportunity to see board fabricators who have micro-via facilities, assemblers with flip-chip equipment, users of chip-scale packages, or manufacturers of alternative substrates, such as ceramic and flexible circuits, then you should grab that opportunity with both hands. If you are short of ideas for a holiday, then you could even choose a holiday destination to suit – micro-vias at South Shields; thick film hybrids in Glenrothes, or flexible circuits on the Isle of Bute. Or you might prefer to tour the States.

For most of you, the tour will be a virtual tour, using Internet resources. However, there are some good books available on these topics and the McGraw-Hill list has many excellent titles.

There are also a number of “roadmaps” that attempt to identify forthcoming developments in technology, equipment and infrastructure. Sometimes such roadmaps are intended primarily for commercial purposes, expressing a marketing intention without necessary underpinning this explicitly. An example is given in the Dyconex Technology roadmap.

Whilst such inputs are useful, more is to be gained from the more formal roadmap process described for iNEMI at this link. Something similar applies to all three of the major technology roadmaps that have been produced covering semiconductors and electronic interconnection. These forecasts of the future, which look in considerable detail at the developments needed to support the technology as well as the technology trends themselves, have become increasingly sophisticated. As indicated in Table 2, the forecasts are sector-specific, rather than general.

Table 2: The iNEMI, ITRS and IPC roadmaps use "product emulators" from these seven sectors to forecast future product needs
Emulators Characteristics
Portable / Consumer High-volume consumer products for which cost is the primary driver, includinghand-held, battery-powered products driven by size and weight reduction.
Office Systems / Large Business Systems Products that seek maximum performance, with cost as a secondary consideration.
Netcom Products* Products that serve the networking, datacom and telecom markets and cover a wide range of cost and performance targets.
Automotive Products Products that must operate in automotive (i.e., harsh) environments.
Aerospace / Defense Products that must operate in extreme environments.
Medical Products* Products that must operate in highly reliable environments.
System-in-Package (SiP)* Complete function provided in a package to system manufacturer.

Whichever road you travel, you can be certain there will be something new around the next bend! So remain aware of the road, look ahead as well as behind, and drive safely!

Supplementary information

Information on the three roadmaps referred to above is at the following links:

International Technology Roadmap for Semiconductors at

IPC 2004-2005 International Technology Roadmap for Electronic Interconnections announced at

International Electronics Manufacturing Initiative Roadmap at

Unfortunately, only the first of these offers a free download of the information, although summaries and comment appear frequently in the trade press.


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