Part 2 of Assignment 2 involves considerable detailed work, which you should be carrying out in parallel with your study of this unit. Of course, the biggest custom component on any assembly is the board itself, and you need to use the information in this unit to choose an appropriate board finish as part of your explanation of the changes needed to the materials purchased (Part 1).
This is a fairly difficult topic for the casual browser to research, so for this Unit, as well as indicating appropriate search terms, we have suggested some specific web-based materials. The resources also include a number of presentations, the first two providing overviews and others giving more process detail.
We hope that you will already have a clear idea of the main board finishes from previous studies, but if you have missed out on these, or need a refresher, there are appropriate links to other AMI material.
A final comment is that, although this unit is headed Implications for board fabrication, some of the topics apply equally to components. After all, most semiconductor components have an encapsulation that is a filled resin, and will absorb moisture in the same way as the printed wiring board, even though their filler is a powder rather than a woven mat. Furthermore, some components, such as the OMPAC BGA and many of the newer chip-scale packages, actually contain a laminated board as part of their structure. There is an interesting (and disturbing) summary of the issues produced by Altera as Challenges in manufacturing reliable lead-free components.
From your study of earlier units you will note that the principal issues affecting the printed circuit board are its solderable surface finish, which now needs to be lead-free, and its ability to withstand the higher temperatures of lead-free soldering. But these aren’t the only issues – take a look at the next set of resource materials, as these will inform our later discussion.
|Martin Goosey’s summary presentation at the April 2004 Northern UK Circuit Group meeting|
Alan Brewin (2003)
|The CAF issue that Alan refers to will be one of the topics in Unit 8|
Alan Rae (2001)
|Note that lead-free is not the only issue of concern to laminate suppliers!|
As well as the requirements for temperature withstand and surface finish, there are environmental challenges, as we saw in Unit 1. If you don’t recall the detail, then follow these links:
The move towards a “green board” is not totally straightforward, particularly when we remember that halogen-free boards have to meet all the requirements of boards made with conventional materials, plus being able to survive the higher temperatures of lead-free soldering. Fortunately, the conclusion from writers such as Neugebauer1 is that the new materials are stable, and likely to be equally reliable. However, mechanical properties will change, the new materials generally having a smaller CTE and greater stiffness.
What effects will the increased temperature of lead-free soldering have on the board laminate?
Before continuing to read further try a search for terms such as:
electronic +laminate +"heat distortion temperature"
electronic +laminate +"heat deflection"
PCB +laminate +decomposition
laminate +"lead-free" +delamination
[Filtering with -package halves the number of hits, a reminder that similar issues affect semiconductor packages]
and then look at these references:
Robert Demaree, Testing thermal stability of bromine-free laminating materials
Park Nelco's Q&A for those involved in Contract Manufacturing
It may be helpful to think of the changes that occur in a laminate exposed to increasing temperature. You will recall that all thermoset polymers have a glass transition temperature (or go to this link to find out what the term means), and that this is below soldering temperature for most materials. This means that, at least for part of the soldering cycle, the board will exhibit an increased CTE and also become softer.
The CTE has a major impact on the reliability of the through-hole connection (for the reasons explained at this link) and the challenge for the fabricator is to deposit a copper through-hole interconnect that is sufficiently ductile to survive temperature cycling – there will be more about this when we consider testing in the next section.
The softening of the board means that the laminate tends to sag during soldering, especially during reflow, where the whole board is subjected to high temperature (Figure 1); after cooling it becomes set in its new, bowed state (Figure 2). Thus, whilst board support has always been a consideration for reflow, it becomes even more important at the higher reflow temperatures required by lead-free solders. [In order to avoid this problem altogether would mean using resins with glass transition temperatures over 250°C, and these have their own problems as well as considerably increased cost]
At the same time as the laminate softens it loses adhesion, mostly between the resin and the copper, but also between resin layers if these are not perfectly bonded. This reduced adhesion may result in delamination if stresses are applied. Stresses may be induced by mechanical means, such as applying a peel force to a pad during rework, or internally by the conversion of moisture to steam, and the build-up of internal pressure. [The same process is referred to as “popcorning” when applied to components such as BGAs] The voids that form are associated with interconnect failure, where either the barrels of the vias crack or continuity to inner layers is lost (Figure 3).
As well as causing internal defects, delamination can appear in surface layers as measles or blistering (Figure 4).
In the same way that components have been claimed to become substantially more moisture sensitive at the higher temperatures of lead-free soldering, board delamination is a potentially serious defect that becomes more likely with lead-free.
Through-hole unreliability and delamination problems are the main issues relating to what Brian Lewis refers to as “laminate thermal robustness” (Figure 5)
However, they are not the only problems to consider. For example, if you have ever seen an assembly that has been trapped in a reflow oven, or used for repeated temperature profiling, you will appreciate that boards tend to discolour with continued exposure to heat, and will eventually decompose. Whilst interconnect reliability is only marginally impaired, the cosmetic effect is not welcomed by customers! Overall, when specifying and evaluating material, one needs to keep in mind any possibility of multiple reflow and rework, and the potential effects that this may have on the laminate as well as the surface finish.
Laminates are complex materials and difficult to characterize; not only are they filled composites, but they may contain a mixture of resins, with each type of polymer having a range of different molecular weights. As one result, the glass transition temperature is really a range rather than a distinct point.
To give another example, if you want to measure the stiffness of a laminate, ‘deflection temperature under load’ is determined by a standardised test2 as the temperature at which a bar of cured bends by a defined amount. This parameter is also called the ‘heat distortion temperature’ (HDT), and is an indication of the extent of cross-linking within the resin. However, this is fairly arbitrary, and it is better to use dynamic mechanical analysis (DMA) to measure the stiffness of the material under a range of loading conditions and temperatures.
2 A number of resin thermal tests are described at this link.
Read the PIAD paper FR4 and PCB: State of the Art given at the MQS Helsinki Conference in 2002. The relevant section starts on p.10
Search for "IST testing". As this generates a large number of hits, try it in combination with T288, for example. You will find one good answer at the Polar Instruments web site.
You will note a number of different tests applied, all of which attempt to emulate the way in which the laminate is stressed during assembly. The test conditions imposed range in severity from relatively mild (though still rapid) temperature cycling, through power pulsing, to immersion in liquid solder. Some of the tests look at microsections to determine whether delamination has taken place; others detect the rapid change of thickness that accompanies delamination; yet others look at the electrical integrity of the via connection. Clearly checking a large number of vias is a more exhaustive test than microsection analysis of a few holes, but the wholehearted adoption of Interconnect Stress Test (IST) does rely on an assumed correlation between IST test results and traditional thermal cycling.
If you want to follow this discussion further, the IPC standard test specifications are available for free download as part of the IPC-TM-650 Test Methods manual at the links given below:
However, for most purposes, the kind of qualification process used by Merix3 – will it survive? – is probably the most practical option for most fabricators.
Steven Schaefer’s paper PWB Dielectric Substrates for Lead-Free Electronics Manufacturing is available from two web sources, both as a formal paper and in magazine format, although the content is the same. Based on a number of tests both for delamination and IST, the conclusion was that performance under lead-free conditions is adequate, although care should be taken with the copper plating.
Davignon & Reed reported4 that the epoxy systems they evaluated discoloured at the higher temperatures used by the NEMI SAC alloy. However, it is worth commenting that the profile used held the boards above the 217°C eutectic for over 60 seconds, and (probably more important) had a peak temperature of 259°C – this is higher than would now be recommended. The researchers also asked (but didn’t answer) the question of whether using a nitrogen environment would reduce the discolouration.
More significantly, whilst the glass transition temperature and CTE of the laminate were little altered, some of the materials tested showed a drop in through-hole reliability, and these changes were related to the chemistry of the material rather than to its glass transition temperature. For example, a high-Tg blend of epoxy and polyphenylene oxide performed less well than a standard FR-4 laminate with a Tg 40°C lower. Whilst their work is a little dated, it does indicate the need to avoid jumping to the conclusion that a high glass transition temperature is necessarily the sign of a more stable laminate.
Finishes (or coatings) on the copper pattern of boards are applied to guarantee good solderability, even after prolonged storage, and to provide the required reliability during product lifetime.
Reflect on your experience with PCBs and board assemblies
|Ken Snowden presentation on Lead-Free Solder Materials (2004)||Slides 16 onwards have information on lead-free board finishes|
Last revised 5 August 2004
Ideally, a board finish should give extremely flat pads, a long shelf life without solderability deteriorating, and high solderability even after multiple soldering cycles, whilst being environmentally friendly and cost-effective to implement. For some discussion on what the surface needs to be flat and solderable, follow these links:
Of course any discussion on solderability raises the twin aspects of:
With other finishes, the mechanisms of solderability deterioration are different: with an OSP coating, the difficulty is one of oxidation of the underlying substrate; with ENIG, nickel diffusion through the pores in the gold is a factor. Whatever the mechanism, the conclusions are the same, that best soldering happens with a virgin surface, and exposure to heat and damp reduces solderability and thus impacts adversely on assembly yield. The inescapable recommendations are to avoid using older boards as far as possible, to take care in storing them, and to use vacuum sealing as far as possible.
Solderability, or rather the lack of wettability, can also result in a solder joint that does not wet the pad completely. This has an impact both on the cosmetic appearance of an assembly and its potential for long-term corrosion. More evident on OSP than with silver-coloured platings, incomplete coverage of the pad is much more common with lead-free solders than with eutectic tin-lead types. Is this a real reliability issue? More in our next Unit!
As well as issues of flatness and solderability, we have identified a number of other requirements for a finish, which include:
The need for this finish to withstand extended heat exposure where multiple reflow is intended or rework is expected. OSP finishes, for example, are known to exhibit problems with second-side reflow.
The finish has to be compatible with a wide range of other metals. For example, a number of OSPs have an adverse impact on gold-plated areas intended for wire bonding and pressure contacts.
Whilst much of the surface finish is removed during soldering, any residue has to be compatible with conformal coating where this is used.
The finish should have a low contact resistance where it is to be used for grounding or shielding applications, and this should not deteriorate with time.
The finish should not impair the reliability of the board – tin whiskers and silver migration will be considered later in this unit and the next.
The finish should also enable the completed assembly to withstand exposure to a hot, moist environment without unacceptable increase in leakage current between isolated conductors. The SIR test, described at this link, is frequently used to verify that the overall assembly meets acceptable criteria.
So, what options are there for surface finish, and what are the problems and pitfalls for the finishes you’ve identified? Look at some of these resources and draw your own conclusions before reading further.
In the past, preferred finishes have been HASL and ENIG. But why these? Tin-lead has been used for many years, because a plated tin-lead coating was already in place as an etch resist, and could be reflowed to provide an economic and solderable finish. The move to lead-free has, however, encouraged the fabrication industry to use tin, so the simple expedient of reflowing is no longer possible. And, in any case, the reflowed finish was very thin, so its life was poor. Hot air solder levelling (HASL) was introduced as an economic means of providing a solderable surface with an even coat. Unfortunately, there are a number of concerns about HASL, relating both to quality and to the control of the process
Electroless nickel immersion gold (ENIG) is a plated but non-fusible finish, and is thus totally flat as deposited; for this reason it has been preferred for fine pitch applications by many users. But, as with HASL, a number of practical problems are associated with its plating chemistry, and there is the severe quality issue of black pad.
ENIG is inherently lead-free, and would appear to be the process of choice. However, black pad is seen as a serious potential danger, and the finish is in any case more expensive than HASL. So is lead-free HASL an option?
The most obvious candidate for the application is the tin-copper eutectic melting at 227°C, as this is substantially cheaper than SAC. Sn0.7Cu has adequate solderability, although the process needs to be carried out at a slightly higher temperature, say 265–270°C, rather than 250–260°C. Provided that the laminate can withstand the temperature, lead-free HASL is viable, but there are practical issues relating to the build-up of dross and to the increase in copper concentration that occurs with use.
Many of the problems can be overcome by using the Nihon Superior alloy, a modified eutectic with a very small percentage of nickel added as a stabilizer, as used for wave soldering.
The problem of copper build-up has already been commented upon, and certainly presents a challenge, especially as the weight of copper dissolved from a bare board will be substantially greater than that which dissolves during wave soldering from a pre-soldered surface and at a lower temperature.
Other alternative finishes include a range of organic coatings that are designed to preserve the wettability of copper surface by preventing oxidation and contamination. However, OSPs that have been designed for use with eutectic solders may not necessarily give the same protection at the higher temperatures required by lead-tin solder, so revised formulations have been necessary, especially for double-sided work. In other respects, current OSPs are similar to the early materials, with the same low-cost benefit, and with the same problems about process control and appearance. Exposed base metal in particular can be a concern for some customers.
One somewhat unexpected problem with OSP has been the increased use of boards with copper pads, but features plated with other materials, especially gold. Traditional OSPs deposit a film on gold that interferes with bonding and probe contact and cause staining of any solder surfaces. Read Improved Organic Solderability Preservatives (OSPs) for Mixed Metal Finishes by Michael Carano and Koji Saeki (CircuiTree, May 2004) to see how materials are being developed to overcome these problems.
Another problem with the OSP type of finish is that the copper surface is not flat on a microscopic scale: there are many fissures, predominantly at grain boundaries, where these finishes are not effective. Plated finishes are therefore highly attractive, although inevitably more expensive, and much effort has been put into alternative plated finishes, both immersion tin and immersion silver – the hyperlinks are to a brief description of each process.
Both finishes have their advocates and their problems, silver with its potential for silver migration, and tin a concern about tin whiskers. These reliability issues will be discussed in the next Unit, but they mostly affect just those surfaces, such as mechanical components, where the final finish is not dissolved during soldering.
A number of comparative studies have been carried out to determine which material should be favoured as a surface finish. An early paper is that by Weissling5, but SMART Group have carried out several comparative tests in the simulated production conditions at InterNepcon Brighton shows. Why not try and draw your own matrix based on their findings . . .
A great deal of work has been carried out by the supplier of surface finishes, and we recommend that you review the information in three key sources. The first of these are recent presentations by chemical suppliers; the third is a seminal paper by Don Cullen published in CircuiTree.
Many of the issues associated with a laminate can be avoided. For example, baking the board before assembly will reduce the risk of delamination caused by absorbed moisture – more information in this paper by Bob Willis.
Similarly, problems due to over-temperature can be mitigated by correct profiling of the reflow process and by taking care over rework. You are recommended to read this NPL Code of Practice for Thermal Profiling Electronic Assemblies and make your own notes on the recommendations for rework practice given in Mark Walz’s Reworking PCBs Soldered with Lead Free Alloys and Lee Whiteman’s Lead-free rework.