Electrolytic plating (‘electroplating’) is a cheap and effective way of building up a layer of copper with almost bulk metal properties. When a direct voltage is applied to two conductors immersed in a solution of a suitable metal salt, current will flow through the solution, and positively charged ions of the metal will be discharged and deposited as a film on the more negative of the two conductors (the ‘cathode’, whence the alternative name of ‘cathodic plating’).
The electrode where electrons enter the solution is termed the ‘cathode’; the one where electrons leave the solution is called the ‘anode’. As electrons are negatively charged, the cathode is rich in negative charge, and the anode is deficient in negative charge. With an applied direct current, ions in the electrolyte tend to move: positively charged ‘cations’ migrate towards the cathode, negatively charged ‘anions’ towards the anode.
Many of the early experiments were carried out by Michael Faraday. His ‘general law of electrolysis’ can be expressed mathematically as the equation:
where W is the weight of substance released, dissolved or deposited; I is the electrode current; T is the time for which that current flows; A is the atomic weight of the substance; Z is the number of electrons involved in the electrode reaction (valency); and F is the Faraday, a constant of value approximately 96,500 coulombs.
The weight of the plating on the cathode is thus a linear function of the product of time and current, typically expressed in ampere-hours1; the average thickness deposited will, however, also depend on the density of the material. The rate of deposition of the most common metals is shown in Table 1.
gm per amp-hour
amp-hour for 25 µm
Note that, in order to plate 25 µm of copper, one needs to apply 1.88 amps per square decimetre (ASD2) for 60 minutes. This relatively slow deposition rate means that plating is usually carried out as a batch process, although, as we will see later, some progress has been made towards implementing continuous horizontal plating lines.
The most common type of copper plating solution is based on copper sulphate dissolved in dilute sulphuric acid. The board to be plated is made the cathode of an electrolytic cell, with a piece of copper as the anode. When direct current is applied, copper is deposited from the solution onto the board, and at the same time an equivalent quantity of copper from the anode is dissolved, maintaining the concentration of copper in solution.
The rate of copper build will depend on geometric factors (where the contact is made, whether shadowing occurs, and so on), and electroplated deposits are not necessarily of even thickness, especially with fine lines and down holes. The problem of reduced thickness is particularly acute with:
The ability of a solution to plate evenly over a large area (‘covering power’), and to plate into holes (‘throwing power’) depends on the current density, the concentration of acid and copper ions, the agitation of the solution, the anode-to-cathode separation, and the bath additives.
The correct selection of suitable additives is what differentiates suppliers of plating chemicals, so there are many combinations, which are formulated for the intended range of current density. There are usually ‘acid modifiers’ to maintain solution stability, ‘levellers’ to block out high current density areas and encourage deposition on the low current density areas, and ‘brighteners’ to modify the crystal structure and give improved elongation.
How much current flows in the cell will depend both on the voltage applied and on the plating cell geometry. Figure 1 is a ‘polarisation curve’, which plots the current in a plating cell against the voltage. The part of the curve3 that we use, the metal deposition area, shows a significant increase of current with applied voltage.
3 A plot of current density, with current density on a logarithmic scale, but concentrating on the linear portion of the curve, is referred to as a ‘Tafel plot’: in 1905, Tafel showed that the over-voltage η in a cell with a high cathodic current is given by the empirical formula
The reason for there being what is called a ‘limiting current density’ 4 is that metal ions cannot be deposited faster than they can arrive at the cathode surface, and this limit is set by the plating bath parameters. If the applied voltage is increased beyond that limit, other reactions will start to occur, such as the evolution of hydrogen. This is usually avoided, not only because it reduces energy efficiency, but because the deposit becomes rough and powdery.
4 There are three major mechanisms by which metal ions reach the cathode surface:
The plating cell potential for any given current is the sum of several types of over-voltage and the ohmic drop in the electrolyte. This ohmic drop depends on the electrolyte conductivity and the distance between anode and cathode. Because both electrodes are good conductors, it can be assumed that the potential between them is the same everywhere. As a result, the current density at any specific local area of the electrode is a function of the distance to the opposite electrode. This effect is called the ‘primary current distribution’, and depends only on electrode geometry and electrolyte conductivity.
The thickness of the local deposit varies with the local time-current product so, as Figure 2 shows, the thickness of the plating can only be constant if the cell geometry creates an even current density.
When plating onto a flat laminate, a sufficiently parallel field can usually be obtained, but plating piece-parts or three-dimensional boards can present more of a challenge. Four general ways of improving the evenness of plating are described below:
All these methods need physical modifications to the plating bath. However, for the more usual PCB situation of a flat substrate, a very simple set-up will provide uniform plating, given attention to agitation. However, this uniformity only applies on a macro scale, and there are a number of causes of small-scale variation, particularly relating to plating down through-holes and vias. Some of these are design-related, and others can be tackled using plating bath additives.
Intuitively, it is easy to see that, the narrower a hole in relation to its width, the less access there will be for plating solutions, the higher will be the ohmic resistance of the path to the anode, and the more difficult it will become to get even plating down the bore of the hole. The measure we use for this is the ‘aspect ratio’. This is the ratio of the depth of a hole to its width: whilst the aspect ratio could be quoted in a number of ways, a fabricator will normally define it as the ratio of the board starting thickness to the nominal drill diameter (Figure 3).
Aspect ratio is a major factor in yields through plating processes, with a high aspect ratio leading to plating ‘voids’ that are not detectable until bare board test. This gets particularly difficult when the holes are small, when the thickness of internal plating becomes even more significant. We reduce the level of this problem partly by design but mostly by adjusting the process.
‘Throwing power’ is calculated as the ratio of the thickness of copper within the hole to the thickness of copper plated onto the surface during the same operation. Typically this ratio will be less than unity, due to the relatively poor access of plating fluids to the hole, and the lower current density within it. The ratio will reduce, to a lesser or greater extent depending on the process, as the aspect ratio of the hole increases (the hole becoming either narrower or deeper).
Because panel plating is carried out before imaging, and is applied to the whole surface, variations in thickness can be kept to less than 10%. However, it is still important to achieve good throwing power so as not to over-plate the surface in the process of getting the desired 25 µm minimum layer thickness in the hole.
With pattern plating, the plating occurs after the image has been created using resist. Patterns are rarely uniform, and may contain both isolated tracks and pads and ground planes. This leads to considerable differences in current distribution, which can result in the copper in isolated areas being substantially thicker compared with those near ground planes. Some of the design issues related to this will be considered later.
Getting an even coat is partly a matter of setting appropriate conditions, and partly of choosing the correct plating additives. We saw from the plot of cell current against voltage in Figure 1 that the part of the curve that we use for plating shows a significant increase of current with applied voltage. It is this curve that can be altered by adding various organic materials to the plating bath:
In writing this, we are not trying to make you into chemists! However, you should be aware than electrolytic plating of copper is not a simple matter of dissolving copper sulphate in dilute sulphuric acid and passing a current between electrodes!
One way to achieve good distribution is to reduce the current density, to perhaps only 15–25% of its nominal level. However, this reduces throughput and increases part cost. In order to plate more quickly, yet achieve high throwing power, there are two options:
The mechanism is that additives are preferentially desorbed from high current density areas during the reverse cycle, which suppresses plating during the forward cycle. The result is substantially improved plating thickness distribution, and sometimes a throwing power of over 100%.
Periodic pulse reverse plating gives excellent results but it does of course mean investment in more expensive power supplies. It also requires specific additives, and is not just a question of changing the plating conditions. As a result, many fabricators prefer to use conventional plating, but pay careful attention to conditions and plating chemistry in order to optimise the uniformity of deposit. As we will see later, there are design strategies that may be used to even out the variation in copper density and thus reduce the importance of the problem.
Conventionally electroplating was always carried out in vertical tanks, with boards moved from plating bath to plating bath by means of programmable hoists. This batch processing made it difficult to integrate within a continuous flow line, and a number of attempts have been made to produce a horizontal electroplating process.
The limitation is that a 60-minute process requires an over-long plating module, so that current density has to be increased substantially, perhaps up to five times greater than for vertical electroplating. This offered a number of challenges to the plating chemist:
These have been overcome by the use of pulse plating to improve throwing power, and by using an insoluble anode and replacing the copper in solution by other means.
The general concept of copper balance is to evenly distribute copper on both sides of the PCB, and also within each side. With outer layers, a balanced copper pattern is important for even plating distribution; for inner layers, the main consideration is to create a balanced lay-up, giving a board that will not warp during subsequent heat processing.
Figure 5 shows ‘before and after’ pictures of an internal PCB layer: before copper balancing the layer has areas with sparse copper tracking that will cause problems for the fabricator; after copper balancing has been added, the previously bare areas have been filled with isolated copper dots.
Plating thickness varies according to the presence or otherwise of adjacent features. In general, it may be said that the more areas you are trying to plate, the thinner the plating will be. Conversely, when plating isolated tracks, the plating thickness can be substantially greater than desired. As shown in Figure 6, although the process conditions are identical, the plating thickness on a track becomes progressively thicker as the track moves further away from other tracks. This can be explained in simplistic terms as being due to the isolated pad experiencing less competition for current and the availability of metal in the plating solution.
But does a thick track matter? Not from the point of view of conductivity, and the extra width will not matter if it is isolated. The main effect will be on the thickness of the solder mask coat: thick copper will give a locally thin coat, with the potential to break down. There is also the mechanical effect on the board, where unbalance may lead to subsequent warpage.
The magnitude of the difference between isolated pads and tracks close together is demonstrated clearly in Figure 7. Not only is the plating on the isolated pad much thicker, with a substantial degree of edge distortion, but the solder mask coating is very much thinner.
Most of the discussion so far has been about copper, but any plating process will have associated potential problems. For example, care has to be taken when tin-lead plating: as shown in Figure 8, over-plating of the etch resist can produce residues of photoresist under the plating ‘overhang’, which will result in unetched areas of foil.
You may have noticed the term ‘well-robbed’ in Figure 7. This is related to the copper thieves referred to earlier, but in this case the additional cathode areas are on the board, rather than in the plating bath. ‘Robbing’ describes the practice of attempting to even out copper distribution on the board by adding areas of spare copper, so that the electrolytic plating process can add equal amounts of copper across the board without creating a thicker copper deposit on less-populated areas. These areas of spare copper are isolated from each other and from any active tracks. Because they act by attracting excessive copper plating away from otherwise isolated tracks, these areas are referred to as ‘robber pads’ or ‘copper thieves’. (Figure 9) The patterns used vary, being sometimes arrays of dots and sometimes cross-hatching.
Explain to one of your colleagues why the thickness of the electroplated layer may vary across a board, the impact this may have on its quality and reliability, and the ways in which designer and processor will seek to combat this variation.
Electroplating needs contact to be made with a fully conductive surface, so can only be used before the board pattern has been etched. Immersion processes (as used for ENIG) work on isolated areas, but this technique can only produce very thin layers. Neither of these processes can create a conductive coating inside a hole: as with a patterned conductor, the hole ‘barrel’ cannot be directly electroplated because the outer conductor tracks are separated by layers of non-conductive laminate.
However, in 1946, scientists experimenting with nickel plating baths, in which a reducing agent was used to inhibit the oxidation of bath constituents, were surprised to find that the amount of metal deposited exceeded that predicted by Faraday’s Law. It was discovered that nickel was being deposited even with no external current, and that plating on a catalytic surface could be brought about by chemical reduction alone. At first, the process was called ‘electrode-less’ plating, but the term ‘electroless’ was soon adopted.
Nickel and copper are the metals most frequently electroless plated, but processes have been developed for tin, tin-lead, cobalt, gold, silver and palladium. One of the advantages of electroless plating is that plating takes place on any activated surface, forming a coating of uniform thickness, and allowing internal surfaces to be plated. The down-side is that the quality of adhesion depends on the nature of the surface, so polished, defect-free surfaces need special chemical preparation before plating.
Furthermore, the materials are expensive, and the process is fairly slow – ‘high build’ solutions can typically deposit 2.5 µm of copper in 15–30 minutes – so, once an initial thin conductive film has been produced, electroplating is generally used to build up the layer.
The internal metallisation of holes is a critical operation, and the electroless copper process which has been developed includes:
Cleaning and conditioning, to remove imperfections and contamination.
Etching, to create the correct surface condition for good adhesion.
Activation, to create a surface which is strongly reducing in nature. [Nascent hydrogen is often liberated at the surface, and agitation may be needed to ensure that the bubbles produced do not mask areas from exposure to the plating solution].
Electroless copper deposition, using a solution containing a source of copper ions, a reducing agent, and complexers and stabilisers to prevent premature precipitation of copper.
For PTH and multilayer boards, a key stage is ‘de-smear’, to remove any friction-melted resin and debris remaining on the inner copper layers after the drilling operation. This can result in open-circuit vias. Frequently de-smear is accompanied by ‘etch-back’ of the base laminate to expose additional internal conductor surfaces.
De-smearing can be carried out using chemical reagents: chromic acid breaks down bonds, making long polymer chains into short ones, but has health and environmental problems; sulphuric acid actually dissolves the epoxy and is less versatile; the permanganate process is very effective, and methods of regeneration have been developed which prevent the precipitation of manganese dioxide sludge. plasma cleaning is becoming popular as a safe and environmentally friendly dry etching process, able to deal with all laminate types. This uses a plasma – a gas containing positive and negative ions as well as free atoms and radicals – to de-smear and etch back drilled holes. The ‘cold’ plasma used for de-smearing is excited by RF energy, and this is usually done in a vacuum chamber, with a low pressure of a suitable gas.
The electroless plating process was developed using formaldehyde. However, this chemical has been classified as a known carcinogen, and can no longer be used without implementing expensive safety precautions including employee monitoring. Anticipating this, plating chemical manufacturers have developed systems with other reducing agents (notably sodium hypophosphite) and a number of alternative ‘direct metallisation’ processes.
An early approach was to use a carbon dispersion to coat board surfaces and hole walls; other systems used graphite, conductive polymers and palladium formulations. Nowadays, a typical process uses a tin-stabilised colloidal palladium dispersion to deposit a film of palladium particles on the surface prior to electrolytic plating. Since this takes place without the evolution of hydrogen gas, holes are more easily accessed and hole walls and vias more evenly plated. The process is complex, involving controlled immersion successively in:
One concern is that direct metallisation processes are not selective, and evenly coat all surfaces, requiring post micro-etches and high pressure spray rinsing to strip off unwanted conductive deposits. However, suitable post dip operations can leave the coating only on the dielectric material, and remove conductive material deposited on the foil interconnect, so that copper is electroplated directly on the foil. This gets round the potential with traditional electroless copper processes for ‘inner-layer separation’ (previously referred to as ‘post separation’), where failure occurs either within the electroless copper layer itself, between the electroless copper and the foil, or between the electroless and the electrolytic copper layers.
Immersion plating is a simple technique for creating very thin coatings, in which the part to be plated is merely dipped in a suitable metal salt. The top surface layers of the substrate are exchanged with metal ions, causing the metal in solution to plate the substrate surface. A classic demonstration of immersion plating is to put an iron nail into a solution of an acidic copper salt such as copper sulphate: iron is dissolved in the solution, and replaced by copper, covering the nail surface with a thin copper layer.
In order for one metal to immersion plate on to another, the metal in solution must be more ‘noble’, or less readily oxidised, than the substrate. This is why gold can immersion plate onto copper, but copper cannot immersion plate onto gold.
A common immersion plating task is to cover a nickel barrier layer with a (more solderable) thin layer of gold. Process control is helped by the fact that immersion processes are self-limiting. However, the very thin deposits are porous, and migration of nickel or copper from beneath the gold surface after plated boards have been subjected to heat processes will have an adverse effect on solderability and/or wire bonding. [Similar, but more immediate, problems are produced by high levels of nickel or copper in the gold plating solution]
Given that electroless plating methods had succeeded in the difficult task of plating down through-holes, it is not surprising that, since as early as 1964, boards have been made by such plating processes, starting with a bare laminate. When electroless plating is used for this purpose, it is often referred to as ‘additive technology’.
There is, however, a major difference between the electroless plating used for through-hole metallisation, which deposits only a very thin layer of copper (0.3–3 µm) as against full electroless plating which has no galvanically-deposited element.
Compared to electrolytic plating, fully-additive technology has several advantages:
Added to the fact that copper is only deposited where it is needed, one might have imagined that additive processes would now be the most widespread. The reason why this is not so relates partly to the higher cost of the processes and partly to a number of process issues:
There are a number of fully electroless processes, which you can find described in Chapter 31 of Coombs 2001, and both panel-plating and pattern-plating variants. Of these, panel plating is most common, in combination with a ‘permanent plating resist’. That is, the plating resist, once imaged and cured, stays as an integral part of the board, and the pattern is plated inside the resist apertures, creating a flush surface, with copper and resist the same height as the laminate. Having this flatter surface reduces scratch damage, reduces the consumption of solder mask, and reportedly tends to minimise solder bridges, particularly for fine-pitch devices.
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