The precursor to modern flip-chip technology was introduced by IBM in 1964 for hybrid modules in the System/360, using copper balls to maintain the separation between die and substrate. This approach evolved into the Controlled Collapse Chip Connection (‘C4’) process, which was patented in 1969. By the 1970s, flip-chips began to find applications in automotive sensors and ignition modules.
C4 technology uses bumps of a high melting solder (97% lead/3% tin) on wettable pads which populate the active area of the chip. When reflowed at high temperature (365ºC peak) the bumps and corresponding metal pads on the substrate reflow to form a electrical and mechanical connection, during which the surface tension self-aligns the chip and board. In order to define the shape of the solder bump, pad limiting metals (PLM) are used to define the wettable area and provide an interfacial barrier protecting the aluminium pad. The flip-chip process is described in Figures 1 to 3.
For the C4 process, the substrate must be able to withstand high temperature processing, so alumina has been the material most commonly used. The interconnection patterns on this can range from single layer to complex multi-layer, with both thin film (vacuum deposited) and thick film (screened and fired) variants.
Substrate pads were originally coated with 90% tin/10% lead solder, but IBM converted some production lines to bare copper in the late 1980s because of process difficulties with increased circuit complexity. The bare copper process avoided tinning problems such as solder shorts.
The original incentive to develop the technology had been to eliminate the high cost, low reliability and poor productivity inherent in manual die and wire bonding. Since then, however, steady advances in machine, materials and vision technologies have made wire bonding both economical and reliable.
In the late 1980s, it was realised that small dense chips were pushing both wire bonding and TAB to their limits as regards performance, quality and manufacturability. Flip-chip technology was seen as a potential solution, allowing chips to be connected directly to a substrate, and eliminating the package. Figure 4 shows that peripheral wire bonds provide greater interconnect density for chips less than 7mm square, whereas for larger chips, flip-chip technology gives more interconnect.
A early (1994) example of the benefits of C4 was the PowerPC 601 microprocessor offered by Motorola and IBM in a C4 form. The performance was enhanced by the change from CSIC to RISC architecture, and the high input/output density and smaller chip size made possible by using C4 technology. At only half the size of the chip used for wire bonding, the C4 version had more than double the number of potential good die per wafer.
Flip-chips have advantages other than interconnection density:
Improvements and innovations which grew from this fresh interest have included the use of organic and glass substrates, alternative bump technologies, and underfilling devices to improve thermal cycling performance.
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A solder bump flip-chip starts with a conventionally processed wafer but builds up a nitride passivation approximately 50% thicker than normal, for added protection. A critical step is anchoring the solder bump, and the ‘under-bump metallurgy’ (UBM) typically consists of three layers:
The aim is to create hemispherical solder bumps of controlled height over each bonding pad. There are a number of processes available for this, but a typical next stage is to deposit solder for the controlled collapse pads and then reflow it in an inert or reducing atmosphere. For high volatility metals, such as lead-tin-silver, it is possible to evaporate hundreds of microns of material, but less volatile metals would take an excessive vacuum deposition time, so electroplating and electroless plating are used for building up higher melting point materials such as gold.
In order to produce the correct eventual profile, solder deposits before reflow are normally larger than the ball limiting pad metallurgy on the wafer. Evaporation of solder was first carried out through metal in-contact masks, but the definition given by this process is inadequate for fine pitch ICs, so in situ polymeric masks are now used.
Figures 5 and 6 and Table 2 describe a typical bumping process, showing the build-up of the metal layers and the reflow process. Part numbers and orientation chevrons can also be applied to the reverse of nitride coated wafers by sputtering a pattern in titanium tungsten. The markings are coated with a thin layer of silicon nitride to protect them and enhance their contrast with the underlying silicon.
|1||A layer of titanium-tungsten is sputtered over the pads to enhance adhesion|
|2||A sputtered copper layer acts as a transition layer for the solder|
|3||The copper layer is etched to form a pedestal on which the solder bump rests - this distributes bump stress so that the adjacent silicon nitride protective coating does not crack|
|4||A layer of electroplated copper is followed by an electroplated layer of tin-lead solder|
|5||Finally the bumped wafers are heated to prevent solder reflow|
Bump adhesion is tested using a shear tester, with the tool brought into contact with the side of the chip. Good adhesion is indicated if the shear strength exceeds 0.8N per bump.
Most solder bumping techniques can only be applied to a complete wafer. Metzger suggested laser chemical vapour deposition (LCVD) as a single-chip bumping process with potential for prototype building and in high mix/small volume applications.
The device is placed in a vapour containing an organo-metallic gold compound. The system is exposed to an argon ion laser beam, which activates the organo-metallic gold compound by pyrolysis or photolysis, or a combination of both, decomposing the material to deposit gold on the laser heated pad. The shape of the bump and growth rate can be modified by changing the deposition time and power, but bumps of 70µm height can be deposited at a growth rate of 6µm/second. By selecting the correct power setting and device temperature, the correct shape and contact wettability can be achieved for subsequent bonding to a gold-plated copper tape, either by gang bonding or single point bonding.
Plating and evaporation are not the only processes: work has been carried out to screen print solder paste (as in BGA bumping) and ‘flattened’ ball bonds (with no tail) give a very high quality high-melting bump for prototype quantities. Table 3 summarises the methods and their respective benefits. Another development has been in depositing solder bumps by ‘solder jetting’, a process which is illustrated in Figs 7 to 10.
|Plating|| Existing, proven process
High capacity (parallel)
| Multiple steps
Not environmentally friendly
|Evaporation||Proven process|| High cost
|Wire bonding|| Useful for prototyping
| Slow, serial process
Not over active areas
|Screen printing|| Proven process
High capacity (parallel
| >600µm pitch
|Solder jet|| Few process steps
Flexible, variable bump size
| New technology
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In the C4 structure, the terminations contain a high percentage of copper which combines during reflow with the tin in the solder to form strong intermetallic. The remaining solder bump is then almost pure lead, creating a very ductile column. However, TCE mismatch between die and substrate places strain on the solder joints, which can result in fatigue failure of the joint during thermal cycling. The strain is proportional to the distance from the ‘neutral point’ at the centre of the chip, so that columns furthest from the centre are most susceptible to failure, and increasing the size of the chip increases the stress experienced.
There are two ways of reducing the level of strain:
It has been observed experimentally that increasing the solder volume, resulting in an increased gap height, improves thermal shock performance, and that early thermal shock failures can be induced by having insufficient solder at the bond pad site.
Both analysis and experiment confirm that the reliability of the assembly can be enhanced by introducing an encapsulant between chip and substrate. This couples silicon and substrate and locally constrains the TCE mismatch, reducing the strain on the flip-chip. Also, by completely filling the space between die and substrate, the area which is stressed becomes the entire die area instead of just the total area of the solder bump cross-sections.
The resin is dispensed in a line along one or two edges of the die and allowed to seep under the die by capillary action. The substrate is heated (typically to around 70ºC) to enhance capillary flow, but the time for underfill to be complete may be as much as 15 minutes, depending on the size of the die. The dispense cycle and line geometry is optimised to allow complete underfill and make a fillet of uniform radius around the complete die perimeter. The encapsulant provides not only mechanical and thermal coupling between die and board, but also forms a protective barrier layer on the active face of the IC chip.
Care has to be taken to avoid contamination which would block the needle or bubbles of air which might become trapped under the die, because large voids in the underfill affect reliability. Where a void totally surrounds a solder joint, that unsupported joint will fail earlier than an encapsulated one, due to fatigue. There may also be what are referred to as ‘pitted voids’ in the area of the solder joints, which are formed by the shadowing effect of the joint on the encapsulant flow. Sometimes solder is extruded into the void, but there is no evidence that this mechanism or these voids cause unacceptable changes in performance.
Most encapsulants used are silica-filled epoxy based materials, with anhydride based curing systems, requiring cures of 1 hour at temperatures of 130–150ºC. Epoxies for this application are supplied premixed and frozen, and have very low levels of ionic contaminants, but are thinner than normal encapsulation compounds, and contain fillers with smaller particles. These fillers modify the TCE of the epoxy to match substrate and die, so that the epoxy does not add to thermal stress.
Filler particles cause difficulty when dispensed under a flip-chip, because filling the gap requires capillary action. Arnold pointed out that the resin and filler have different densities and flow characteristics, so that laminar flow cannot occur with a filled material. Whilst pre-heating filled encapsulants may increase the flow rate of the organic portion, this also reduces the ability of the resin to move fillers through the gap. In theory the result could be uneven distribution under the chip, causing thermal stress because of the TCE imbalance. In practice, Baggerman reported that, with a chip to polyimide gap of only 55µm so that filler particles were excluded, no failures were observed after 2,000 thermal cycles. Perhaps the most important factor is that the whole of the volume should be filled with resin. However, a real disadvantage of a rigid epoxy underfill is that it is sensitive to gross distortion of the substrate.
Arnold suggests the use of aerobic urethane underfills, which combine high adhesive tensile strength with high elongation. A soft and flexible urethane backbone acts as a shock absorber, effectively dissipating both mechanical and thermal shocks. In contrast, a brittle epoxy can be more rigid than solder or bond wires and would transfer stresses to these parts of the assembly.
Arguably there may be a real choice between using materials with high adhesion and low modulus, and selecting more rigid materials, provided that these are adequately matched. Goldstein found that, when subjecting underfilled samples to 1,000 thermal cycles, the change in measured characteristics was lowest for the samples underfilled with resin having a TCE most similar to that of the solder. O’Malley suggests that it is the underfill chemistry which is critical, as it affects the adhesion of the encapsulant to the chip surface. Experiments must be carried out to verify the choices made.
When an underfilled flip-chip assembly is tested to destruction by thermal cycling, the dominant failure mode is delamination of the interface between the active face of the die and the underfill. Once adhesion between these surfaces is lost, the flip-chip joints are directly subjected to the strain resulting from the thermal mismatch between die and board. Electrical failure follows shortly after delamination as the result of solder fatigue cracking (Figure 11).
The number of thermal cycles required to initiate failure can vary greatly, depending on the materials used and the process parameters, but flip-chip assemblies routinely survive 2,000 cycles from −40ºC to +120ºC with no failures. In fact, flip-chips have been claimed to be more reliable than conventionally packaged devices, reputedly due to freedom from gold-aluminium intermetallic growth catalysed by trace quantities of halides in the packaging.
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The term ‘flip-chip on board’ (FCOB) refers to the interconnection of unpackaged integrated circuits directly on an organic substrate. Whilst the die bumps are still of 97% lead/3% tin alloy, the corresponding sites on the substrate are selectively coated with low melting 60% tin/40% lead solder. After the flip-chip has been aligned and placed on the substrate, active face down, it is then reflow soldered in a conventional surface mount reflow oven. The low temperature solder alloy on the board reflows, wets around the high temperature bumps on the IC, and forms the interconnect between the chip and the board. The high temperature solder on the chip does not reflow, giving a defined stand-off between chip and board, and the assembly can be reworked if necessary (Figure 12).
O’Malley found that there were considerable differences between nominally identical boards supplied by different vendors. Investigating indicated that improved performance depends on:
Flip-chip technology allows the designer the freedom to connect anywhere on the die surface, and C4 bumps can be placed over most circuitry. FCOB bump diameters are 100–150µm; typical joint heights between 70–80µm, being determined by bump diameter, the number of bumps, the mass of the chip, and the diameter of the substrate pad. The self aligning characteristic of a flip-chip requires placement accuracy of one half the width of the solder pad on the board, or ± 70–100µm.
Figures 13 & 14 show the trends in bump diameter and pitch for assemblies on ceramic and printed wiring board. DeHaven’s expectation (1994) was that ceramic would remain the primary substrate medium for high performance products.
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Many technologies have been developed as alternatives to the solder-based C4 process used by most production systems: solders tried include indium/lead alloys to provide enhanced fatigue resistance; other metallisation systems use gold thermocompression or thermosonic bonding; various conductive polymers have recently been evaluated. The section below contains examples of some of these alternatives.
It should be kept in mind that most proposed systems have limitations:
Goldstein describes a method which combines substrates electroplated with bumps of 95% lead/5% tin solder capped with an indium layer with gold bumping of the dice, which can be carried out on either the entire wafer or on a single die as small as 3.5mm.
The substrate is heated to a temperature below the melting point of indium (160ºC) and the chip to a temperature above it: when the hot gold bump comes into contact with the solder, the indium melts, forming a metallurgical connection without needing flux.
Where the die performance is unknown, the chip can be ‘tacked’ to the indium cap using very little pressure (5 gm/bump), to give a temporary bond with a very low resistance (less than 10mΩ) for electrical test, yet leaving the solder bump with only minor damage so that the chip can be removed and replaced. Chips shown to be functional after test can be attached permanently either by a second pass on the alignment equipment or by heating in a reflow oven. This overcomes the disadvantage that, as with wire bonding, it is not possible to perform burn-in or full test on a flip-chip in die form.
In normal reflow processes, the pads on chip and substrate self align because of surface tension in the solder. However, in this case, the temperature remains below the melting point of the lead tin solder (325ºC) so that surface tension forces cannot operate, and the placement machine needs to be highly accurate.
Philips use a gold tin metallisation system for the flip-chip bonding of integrated circuits onto flexible polyimide substrates. The gold bump on the chip guarantees a defined stand-off height, and the tin required to create a gold-tin solder between the chip and copper tracks can be deposited on either the bump or the tracks. Soldering is carried out using pulsed heat thermode (gang) bonding.
EDX measurements indicate that a eutectic (80/20) gold-tin or Au 5Sn phase is required for good quality bonds, and the initial quantity of tin has to be controlled to achieve this.
Because of the large thermal mismatch and small stand-off height of the IC, the number of cycles to failure during temperature shock is limited, the first ruptures occurring after 50 cycles, but this is improved by a factor of 20 by using an epoxy-based underfill material.
The layout of the copper tracks on the reverse side of the foil also strongly influences the number of cycles to failure. Foils with a large built-in flexibility have better reliability behaviour, and flexibility is limited by having wide copper tracks on the reverse side.
AT&T Bell have evaluated anisotropically conductive adhesive for flip-chip attach. Using a thixotropic paste, instead of the more conventional film form, allows the adhesive to be stencil printed. Chips placed into the paste are held by its ‘tack’, in the same way that surface mount components are held by solder paste. As a result, no heating of the chips is required during placement, increasing throughput and relaxing coplanarity tolerances in the alignment equipment.
As with all anisotropically conductive materials, the paste has to be cured by simultaneous application of heat and pressure during a 3–5 minute cure cycle. AT&T Bell carried this out using a fixture holding multiple chips and applying uniform pressure with a conformable silicone rubber bladder. Using chips with gold metallisation, the increases in contact resistance were less than 15% after 1000 test cycles between 0–100ºC. However, aluminium metallised chips proved to be unreliable.
A number of techniques for solderless interconnection have been prompted by LCD development:
Philips have used chip on foil technology to connect to Indium-Tin-Oxide contacts on the LCD. By mounting the circuitry on the foil connector to the LCD, the overall system is very much thinner than PCB mounted displays, and fewer connections enhance reliability.
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