Topic

The Chip-Scale Package

Introduction

Market pressures have forced semiconductor manufacturers and assemblers to consider ways in which the overall size of electronic assemblies can be reduced, and the many attempts made have resulted both in the development of smaller packages and in the complete removal of the package.

Whilst in theory it is cheaper to mount the chip directly onto the board, there are a number of practical issues in achieving Direct Chip Attach at high yield and without incurring cost penalties. Whilst the technique is used for specialist applications both on ceramic substrates (‘hybrid circuits’) and on flexible printed circuit (COF = ‘Chip-on-Flex’), the direct-mounting approach on conventional laminate is relatively uncommon.

Part of the reason is that, by the time the die and its associated wires have been protected by ‘glob-topping’, the space taken may actually be larger than when using a package, certainly for devices with a small number of leads. But there are other practical considerations:

This list has been arranged in increasing order of cost and difficulty and the KGD problems, which affect yield and cost, are well-known, as a web search will verify. The consequence is that Direct Chip Attach is usually only available from specialist contractors, and most assembly line managers will do anything to avoid using the technology! And that reluctance also applies to the use of flip-chip devices, although there are fewer process problems than with die and wire bonding.

Fortunately for the industry, at the same time as the problems of DCA were being encountered, considerable advances were being by component suppliers. Whilst market-driven, small packages have also been technology-enabled:

In consequence, over the past 25 years, many thinner, smaller packages have been developed.

A further technology change that has militated against Direct Chip Attach has been the emergence of the area array, which improves assembly yields and makes it possible to mount devices with very large numbers of leads.

All these changes in package design have produced parts for conventional assembly that are increasingly close to the size of the die inside the package. The range of products that moved towards this goal were first called ‘chip-scale’ in the early 1990s, and the title ‘Chip-Scale Package’ (or Chip-Size Package), contracted to CSP, has been in common use since the mid-1990s, spawning a magazine in the process, and being the title of John Lau’s seminal book.

During the practical realisation of the concept an enormous number of different designs have been developed – in fact, John Lau’s book contains one chapter of introduction, and no fewer than37 supplementary chapters, each dealing with a different design . . . and a few years afterwards, one reporter referred to there being over 50 distinguishable types. Fortunately, there has been some ‘weeding out’ of the more complex and impracticable suggestions, but there are still many design approaches and a bewildering number of acronyms.

As an introduction to Chip-Scale Package, it is worth carrying out a preliminary web search, examining the different CSP types, and seeking to understand how they are made. After all, as with all other electronic components, having an understanding of the product will help us use it properly and avoid application problems.

Exercise

For this exercise, carry out a search using terms such as CSP or "Chip-scale package":

  1. Tabulate the various CSP constructions, describing the unique aspects of each type, and including any cross-references to specific companies.
  2. What are the general manufacturing methods and materials used for their construction?

A wealth of resource is available, perhaps overmuch information! Device manufacturers and specialist assembly houses present considerable information on their websites. Examples are:

http://www.ti.com/
Search with "Chip-scale package", or you get 25k+ results!

http://www.tessera.com/
Lots of good information

Amkor http://www.amkor.com/

Flip Chip International http://www.flipchip.com/

The archives of two trade journals are also helpful:

Chip Scale Review magazine (archives back to 1998!) http://www.chipscalereview.com/

Advanced Packaging magazine http://ap.pennnet.com/home.cfm

 

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CSP defined

During your web search you will probably have come across a formal definition of what ‘chip-scale’ means. This derives from IPC, and defines a chip-scale package as one whose linear dimension is less than 1.2× the die dimension, or (probably more useful) where the area of the packaged part is less than 1.5× that of the bare die.

However, that definition precludes space-efficient versions of simple products such as transistors and diodes where the die itself is very small, so that CSP is unachievable. Yet having the smaller part available may be attractive to the designer. In our view, whilst CSP is a well-understood term, we should not lose sight of the real aim, which is volume-efficient encapsulation of an active component, producing a part that is easy to assemble by conventional soldering techniques but with minimal packaging ‘overhead’.

If you haven’t yet come across the link to http://www.semiconfareast.com/csp.htm during your web search, you are commended to read it, if only for the following quotation:

Quote

“Because of this variety of chip scale packages developed in the industry, one can not make any generalized assumptions on the manufacturability or reliability of the CSP as a homogeneous package group. It is often necessary to determine what the structure of the CSP is before any conclusion on its robustness or manufacturability can be made.”

Chip Scale Package - CSP - Page 1 of 2 at http://www.semiconfareast.com/csp.htm
(Page 2 may be found at http://www.semiconfareast.com/csp2.htm)

 

This quotation is a warning that the term CSP covers a broad range of products, not all of which will meet our requirements for manufacturability and reliability. Read Paul Magill and Joseph Baggs CSP Present and Future (http://www.unitive.com/casestudies/pdfs/csp.pdf) for an insight into what we are looking for in a CSP, and consider the extent to which the designs you have explored approach the ‘ideal CSP’.

Apart from the general ‘grey area’ between CSP and ‘thinner, smaller’ packages (especially for discrete devices), there are three respects in which the boundaries between CSP and other technologies are poorly-defined:

Between CSP and flip-chip. Does the fact that the bumping is carried out after fabrication make the flip-chip a CSP? Our view is that it does not. Whilst flip-chips need processes other than soldering, such as underfill, so do many miniaturised area arrays, but there is a real distinction, in that flip-chips have no ‘interposer’ between semiconductor die and board. Also, flip-chip technology is itself used in the construction of a number of different chip-scale packages.

Between CSP and advanced, complex packages such as System-in-Package (SIP) and Wafer Scale Packaging (WSP). Here we would regard the point of differentiation as being whether the package contains a number of support components, rather than a single semiconductor.

Whether CSP constructions containing a number of packages stacked together are genuine CSPs, or whether they should be regarded as three-dimensional Multi-Chip Modules. Here we would accept packages such as the stacked SOC package as being CSPs, given that they are sold as individual devices and contain no support components.

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Package configuration

Given the very wide range of different packages, it is hardly surprising that we should attempt to categorise chip-scale packages in some way. We suggest three ways of discriminating between CSP designs that are useful for different purposes:

Intended use – what market or application is the CSP designed to meet? What types and sizes of die can be fitted in the package? And how many external connections are available?

For example, there will be significant differences between the requirements of products such as memory (large die; high volume; few bonds) and ASICs (die of variable size; small volume; a large number of bonds)

The basic technology used within the package – whether the chip is face-up or face-down; the materials and design of any lead frame or equivalent; the method used to connect to the die face; the form and application method for the encapsulant.

The package configuration – whether the CSP presents the assembler with leads, balls, or solderable areas on the package.

When you were reading the paper by Magill and Baggs, you may have noticed Figure 2, which contained a large number of different CSP types and manufacturers, but was organised in four generic groups corresponding to the basic technology used for the package. This reflects a very similar grouping in John Lau’s book Chip-Scale Package, and is primarily based on the form of the interposer that distributes the connections between die and outside.

The list below contains links to supplementary papers that illustrate the different packages, and we recommend you to browse these (rather than printing them) to gain some appreciation of the general format for each style of CSP and its application area, and of the assembly techniques involved. Bear in mind that the material was taken from John Lau’s book, and there has since been a considerable development and simplification. You will probably be able to deduce which of the approaches is still reflected in a current product, and which ideas have “bitten the dust” on account of their complexity or practical manufacturing issues.

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Materials and manufacture

With the exception of the materials used for wafer-level redistribution, the range of materials and processes used is typical of those employed in conventional semiconductor components. The table below is a good summary of the main options.

package structural element selected options
leadframe packages
leadframe metal Alloy 42 kovar copper
leadframe inner lead finish silver gold palladium
wire gold aluminium copper
encapsulant epoxy silicon polyimide
leadframe outer lead finish solder nickel-palladium gold
laminate packages
laminate type BT polyimide high-temp FR-4
redistribution metal copper gold nickel
wire gold aluminium copper
encapsulant epoxy moulded epoxy glob top epoxy underfill
inner I/O finish gold nickel-palladium silver
outer I/O finish solder ball nickel-gold silver
ceramic packages
substrate alumina aluminium nitride beryllia
metal thin film copper thick film copper thin film gold
wire gold aluminium copper
finish Au solder nickel-palladium
encapsulant none (lidded) silica gel epoxy underfill
wafer-level packages
build-up polymer BCB1 polyimide epoxy
redistribution metal copper aluminium gold
encapsulant epoxy silicon BCB
bump contacts solder copper nickel-gold
Joseph Fjelstad, Materials and Methods for IC Package Assemblies,
Advanced Packaging, August 2005
1 BCB = benzocyclobutene (see Ying-Hung So et al, Benzocyclobutene-based polymers for microelectronics, in Chemical Innovation, December 2001 at http://tinyurl.com/ex6cb)

 

Note that in each case there is a range of options, of which that most commonly selected will be found in the left-hand column. Specific points to note are the use of bismaleimide triazine resin for interposer laminates, resulting from the extended experience with that material as part of the OMPAC BGA package.

Given the smaller dimensions of CSPs, especially thickness, structures may be expected to be more sensitive to moisture and over-temperature, both of which will impact on the material choice as well as the design. Also, given the smaller dimensions of many of the piece parts, changes may be needed to the manufacturing processes, for example using etched rather than stamped leadframes.

There is some variation in the technologies used, depending primarily on the form of the interposer and whether flip-chip is used to replace wire-bonding. Whilst the techniques are the same as for larger packages, some adaptation may be required on account of the smaller size. Examples of this as they relate to the QFN package, one of the main runners, are given in the paper by David Comley and Paul Smith, The QFN: Smaller, Faster and Less Expensive, published in Chip Scale Review Online in August 2002.

Note the additional procedures such as polyimide taping, and the emphasis on tight process control (for example during sawing), needed to get a good yield. Edward Combs, in Leadless plastic packages, such as the DFN and QFN, have inspired a renaissance in a mature technology (Chip Scale Review Online, March 2003), also indicates that additional processes may be needed for package singulation. The upshot is that, despite the benefits to the designer of using a smaller package, the cost of manufacture of the piece-part itself may be higher.

Making CSPs presents challenges even for packages based on the lead-frame, although these are conceptually similar to conventional plastic-encapsulated microcircuits. A useful discussion on this topic by Paul Smith in his Challenges of Leadframe-Based Micro-Packages, published in Chip Scale Review in November 2005.

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Using CSPs

In the first search task we asked you to concentrate on the types of CSP and on the manufacturing methods used in their construction. Having tried to classify the types of part used, and discussed the issues involved in manufacture, it is time to look at the practicalities of using CSPs. For example, would you expect them to be significantly different to other solderable surface-mount parts?

Exercise

Before offering our own comments, we would like you to repeat the earlier search task, but this time concentrate on issues relating to design and use:

  1. What factors that might affect the assembly process are associated with each style of CSP?
  2. What might be the impact of using CSPs from the perspective of the board designer?

 

Packaging and presentation

The challenges that the use of CSPs present to an assembler are in general an amplification of existing issues rather than anything particularly novel. For example, as with any small package, the stencil design needs to be correct, and both printing and reflow optimised. Also, placement equipment needs both to achieve tight tolerances on positioning and have its vision systems tuned for components with under-body features rather than leads.

Supplementary information

Further information on these issues in:

Tim Jensen and Ronald Lasky, Assembling Chip-Scale Packages with high yields requires care with printing and reflow processes, Chip Scale Review Online, November 2002.

Robert Bertz, How the spiraling growth of leadless packages is challenging tape-and-reel processing, Chip Scale Review Online, October 2002.

 

One potential point of difference is in the way that components are presented for assembly, as in some cases conventional pocketed tape is not suitable for the components. A useful alternative approach is discussed in the TI application note on Surftape Carrier Tape.

Assembly

Whilst one of the aims suggested in the Magill and Banks paper is that no underfill should be necessary, in practice many CSP styles exhibit improved reliability if a suitable material is used to fill the space between the part and substrate. This is particularly true of parts such as microBGAs, where the stresses have otherwise to be absorbed across only a small contact area. More information on this in our topic paper on Flip-chip in the section on Underfilling.

Comment: parts that are fully underfilled are almost impossible to rework satisfactorily, and an alternative is to use a corner-bonding underfill process, such as that described by Brian Toleno and Josef Schneider in Processing and reliability of corner-bonded CSPs (Advanced Packaging, March 2004).

Reliability

Underfilling is a way of improving reliability, and the rationale for doing this is to improve resistance to solder joint failure when exposed to extended temperature cycling. In his paper Board-level Reliability Design (Advanced Packaging, June 2003), Tong Yan Tee, builds fatigue models against which he is able to assess the effects of changes to key parameters. He found relationships between fatigue life and:

All of these tie in with intuitive expectations based on an understanding of the structures, but are nonetheless valuable in alerting the designer to a potential reliability consequences of selecting a particular design.

Benefits

Despite there being some reservations about the reliability of the CSP, both microBGAs and leadless packages based on an internal leadframe have proven very popular with designers and assemblers. Compared to direct chip attach, they are easier to assemble and rework, and the parts can be fully-tested and burnt-in before assembly if this is required. The die protection is also better, and does not need to be added by the assembler.

There may be some applications in which a chip will give better electrical performance when directly mounted on the board, and the assembly may be slightly lighter than when a package is used, but the relative costs are arguable. So too is the comparison of their thermal performance. Particularly with the QFN, where there is an easy route through the base to the board, the package part is only marginally less effective thermally than direct chip attach, and it is considerably better than conventional packages, as Comley and Smith show in their paper The QFN: Smaller, faster and less expensive (Chip Scale Review Online, August 2002).

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The future

So, what is the future for the chip-scale package? To judge from the paper by Fan and McLellan (Leadframe Chip Scale Packaging, Advanced Packaging, July 2003), the future is all QFN! Their view is based on a favourable comparison of thermal resistance and electrical inductance and the fact that the QFN package is easier to route than area arrays. Fan and McLellan see the next step on the evolutionary path as being the chemically-milled package, which extends the I/O count by using multiple rows of connections, whilst retaining the simplicity of the lead-frame CSP.

Tuckerman (Looking into the future of Chip-Scale Packaging: What’s next for this still-evolving technology?, Chip Scale Review Magazine, July 2005) is more wide-ranging in his review of the CSP challenge, and sees continuing trends to finer pitch and thinner parts, as well as a demand for the stacking of multiple chips to increase functionality. [Building in three dimensions is a topic that is further discussed in AMI4945 Unit 11]

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